Clock phase detecting circuit and clock regenerating circuit each arranged in receiving unit of multiplex radio equipment

ABSTRACT

The present invention relates to a clock phase detecting circuit and a clock regenerating circuit each arranged in a receiving unit of multiplex radio equipment. The receiving unit of the multiplex radio equipment includes an identifying circuit for identifying a signal obtained by demodulating a multilevel orthogonal modulation signal; a clock regenerating circuit for regenerating a signal identification clock for the identifying circuit to supply the clock to the identifying circuit; an equalizing circuit for subjecting the signal obtained by demodulating a multilevel orthogonal modulation signal to an equalizing process. A clock phase detecting unit detects the phase component of the signal identification clock based on signals input to or output from the equalizing circuit and then supplies the phase component to the clock regenerating circuit. The phase component of a signal identification clock can be certainly detected and accurately adjusted so that the signal identification clock can be regenerated with high accuracy.

BACKGROUND OF THE INVENTION

1) Field of the Invention

The present invention relates to a clock phase detecting circuit and aclock regenerating circuit each arranged in the receiving unit inmultiplex radio equipment.

Generally, the clock regenerating circuit which is used in the receivingunit of multiplex radio equipment is called a BTR (Bit Timing Recovery)circuit. The clock regenerating circuit usually regenerates a clockcomponent based on a signal obtained by demodulating a multilevelorthogonal modulation signal obtained through PSK (Pulse Shift Keying)or QAM (Quadrature Amplitude Modulation) and then supplies it as anoperation timing signal for an identifier (e.g. an A/D converter) thatmainly identifies received data (signal).

The clock which is regenerated in the clock regenerating circuit must beagreed in phase with a demodulated signal level identifying timing (whenthe so-called eye-pattern is most opened). However, a change in trunkstate due to temperature changes may cause a deviation in phase of aclock pulse.

Hence both a clock phase detecting circuit that can detect a phasedeviation with high accuracy and a clock regenerating circuit thatadjusts accurately a deviation in phase of the clock detected by theclock phase detecting circuit and then supplies signal identificationclocks with high accuracy have been requested.

2) Description of the Related Art

FIG. 60 is a block diagram illustrating the configuration of a clockregenerating circuit arranged in the receiving unit of a generalmultiplex radio equipment. Referring to FIG. 60, numeral 71 representsan orthogonal detecting unit; 72 and 73 represent A/D converters; 74represents a transversal equalizer; and 75 represents a clockregenerating circuit.

The orthogonal detecting unit 71 detects a signal (IF (intermediatefrequency) signal) obtained by demodulating a multilevel orthogonalmodulation signal due to PSK or QAM and then produces two kinds ofbaseband signals (an Ich signal and a Qch signal) with a different angleof 90° in phase from each other. As shown in FIG. 60, the orthogonaldetecting unit 71 is formed of hybrids (H) 711 and 712, phase detectors713 and 714, roll-off filters 715 and 716; and a local oscillating unit717.

In the detecting unit 71, the hybrid 711 splits the IF signal input intotwo components and then sends respectively to the phase detectors 713and 714. At this time, the local oscillating unit 717 supplies a carrierregenerating signal synchronized in phase with a carrier wave to thehybrid 712. The hybrid 712 splits the carrier regenerating signal intotwo signal waves with phases different from each other by 90°: one beingoutput to the phase detector 713 and the other being output to the phasedetector 714.

As a result, the phase detectors 713 and 714 receive base band signals(an Ich signal and a Qch signal) having phases different from each otherby 90°. The A/D converter (identifying unit) 72 receives the Ich signalvia the roll-off filter 715 to perform an A/C conversion (signalidentification). The A/D converter (identifying unit) 73 receives theQch signal via the roll-off filter 716 to perform an A/D conversion(signal identification). Thus digital demodulated signals with phasesdifferent from each other by 90° are obtained.

The A/D converter 72 converts the Ich signal from the orthogonaldetecting unit 71 to a digital demodulated signal by A/D converting at apredetermined signal level. The A/D converter 73 converts the Qch signalfrom the orthogonal detecting unit 71 to a digital demodulated signal byA/D converting at a predetermined signal level. The transversalequalizer 74 equalizes each the digital demodulated signals from the A/Dconverters 72 and 73.

The clock regenerating circuit 75 regenerates A/D conversion clocks, ofwhich the timing at which the A/ID A/D converters 72 and 73 execute anA/D conversion (the so-called eye pattern in fully opened state) matchesthe phase, from a received signal to be detected by the orthogonaldetecting unit 75 and then supplies them respectively to the A/Dconverters 72 and 73. The clock regenerating circuit 75 is formed of asquare detecting unit 76, a filer 77, and a PLL circuit 78. The PLLcircuit 78 is formed of a phase detector (PD) 79, a loop filter 80, anamplifier 81 and an oscillating unit 82.

The square detecting unit 76 subjects a signal to be detected by theorthogonal detecting unit 71 to a square detection. The filter 77filters the output of the square detecting unit 76.

In the PLL circuit 78, the phase detector 79 phase-compares the signalsquare-detected by the square detecting unit 76 and input through thefilter 77 with the A/D conversion clocks output from the oscillatingunit 82 for the A/D converters 72 and 73 and then feedbacks the resultas a control signal to the oscillating unit 82 via the loop filter 80and the amplifier 81. As a result, the clock (an A/D conversion clock)following the phase of a signal to be detected by the orthogonaldetecting unit 71 can be obtained.

In the clock regenerating circuit 75 having the above-configuration, theA/D conversion clocks for the A/D converters 72 and 73 following thephase in which the eye pattern of a received signal is most opened areregenerated from the signal to be detected by the orthogonal detectingunit 71 and then sent to the A/D converters 72 and 73, respectively.Then each of the A/D converters 72 and 73 can regenerate the receivesignal data through an accurate digitalizing process.

The clock regenerating circuit 83 proposed by Japanese Patent Laid-openPublication (Tokukaisyo) No. 63-215235, as shown in FIG. 61, is formedof a phase deviation detection unit 831, a an infinite phase shifter832, and an oscillating unit 833. Numeral 81 represents a demodulatingunit which demodulates a received signal and 82 represents a dataregenerating unit that regenerates a demodulated signal (data) from thedemodulating unit. The data regenerating unit 82 consists of anequalizer (EQL) 821 that subjects a demodulated signal to an equalizingprocess and an identifier (A/D converter) that identifies and encodes(digitalizes) the level of the demodulated signal processed by theequalizer.

In the clock regenerating circuit 83, the phase deviation detecting unit831 monitors the output signal from the identifier 822 and then detectsthe deviation between the signal phase of the most suitable identifyingtiming in the identifier with the phase of the clock (CLK). The infinitephase shifter 832 provides a phase shift to the signal with a fixedfrequency from the oscillating unit 833.

In the clock regenerating circuit 83 with the above-mentioned structure,the phase deviation detecting unit 831 detects a change in phasedeviation appeared between the timing to be identified by the identifier822 and the clock (CLK) supplied as an operation timing of theidentifier 822, and the infinite phase shifter 832 phase-shifts theoutput of the oscillating unit 833 synchronous with the change in thephase deviation. Thus the phase deviation is canceled so that the clockmatched with the phase of the identification timing can be regeneratedcertainly.

However, the clock regenerating circuit 75 shown in FIG. 60 regeneratesan A/D conversion clock each for the A/D converters 72 and 73 from asignal to be detected by the orthogonal detecting unit 71, or an analogsignal, thus tending to be frequently influenced by the trunk status dueto temperature changes or the like. As a result, there is a problem inthat the A/D conversion timing of each of the A/D converters 72 and 73can not be agreed with high accuracy with the most suitable timing inwhich the eye pattern of a received signal is most opened.

As described above, regenerating the A/D conversion clocks from ananalog signal leads to the clock regenerating circuit 75 in an analogconfiguration, as shown in FIG. 60. Hence, there is a problem in thatthe analog configuration results in a large circuit scale in addition toa large number of manual adjustments.

On the other hand, in the clock regenerating circuit 83 shown in FIG.61, the phase deviation detecting unit 831 detects a change in phasedeviation and the infinite phase shifter 832 phase-shifts the output ofthe oscillating unit 833 in synchronism with the phase deviation change.Thus the clock agreed with the phase of the identification timing can becertainly regenerated by canceling the phase deviation. However, thephase deviation detecting unit 831 detects a phase deviation withinsufficient accuracy rather than high accuracy. Hence there is aproblem in that the operation timing of the identifier 822 cannot becompletely agreed with the most suitable timing in which the eye-patternof a received signal is most opened.

SUMMARY OF THE INVENTION

The present invention is made to overcome the above mentioned problems.An object of the present invention is to provide a clock phase detectingcircuit arranged in the receiving unit of multiplex radio equipment thatcan regenerate a signal identification clock with high accuracy bycertainly detecting the phase component of a signal identification clockand then accurately adjusting the same.

Another object of the present invention is to provide a clockregenerating circuit arranged in the receiving unit in multiplex radioequipment that can regenerate a signal identification clock with highaccuracy by certainly detecting the phase component of a signalidentification clock and then accurately adjusting the same.

In order to achieve the above objects, according to the presentinvention, the clock phase detecting circuit arranged in a receivingunit of multiplex radio equipment, is characterized by an identifyingcircuit for identifying a signal at a predetermined identificationlevel, the signal being obtained by demodulating a multilevel orthogonalmodulated signal; a clock regenerating circuit for regenerating a signalidentification clock for the identifying circuit to supply the clock tothe identifying circuit; an equalizing circuit for subjecting thedemodulated signal obtained by demodulating the multilevel orthogonalmodulated signal to an equalizing process; and a clock phase detectingunit for detecting a phase component of the signal identification clockbased on input/output signals of the equalizing circuit and then forsupplying the phase component to the clock regenerating circuit.

Hence, in the clock phase detecting circuit arranged in the receivingunit of the multiplex radio equipment according to the presentinvention, the clock phase detecting unit can detect the phase componentof a signal identification clock, based on the input/output signals ofthe equalizing circuit which subjects a signal obtained by demodulatinga multilevel orthogonal modulated signal to an equalizing process andthen supply it to the clock regenerating circuit. Hence there is anadvantage in that the clock regenerating circuit can adjust veryaccurately the phase component of a signal identification clock, thusgreatly improving the performance of the multiplex radio equipment.

According to the present invention, the clock regenerating circuitarranged in a receiving unit of multiplex radio equipment, the receivingunit including an identifying unit for identifying a signal at apredetermined identification level, the signal being obtained bydemodulating a multi-level orthogonal modulated signal and an equalizingcircuit for subjecting the demodulated signal to an equalizing process,the clock regenerating circuit regenerating a signal identificationclock for the identifying circuit an then supplying the signalidentification clock to the identifying circuit; , is characterized by aclock regenerating unit for regenerating the signal identification clockbased on a signal before the multilevel orthogonal modulated signal isdetected; , a phase adjusting unit for adjusting the phase of a clockfrom the clock regenerating unit and then supplying the phase-adjustedclock to the identifying circuit; , and a clockphase detecting unit fordetecting a phase component of the signal identification clock based oninput/output signals of the equalizing circuit and then supplying theresult as the phase adjustment control signal to the phase adjustingunit.

In the clock regenerating circuit arranged in the receiving unit of themultiplex radio equipment according to the present invention, when asignal identification clock for the identifying circuit is regeneratedfrom a signal before a multilevel orthogonal modulated signal isdetected and the phase adjusting unit adjusts the phase of the clockfrom the clock regenerating unit and then supplies the result to theidentifying circuit, the clock phase detecting unit can detect the phasecomponent of the signal identification clock, based on the input/outputsignals of the equalizing circuit, and then supply it as a phaseadjustment and control signal to the phase adjusting unit. Hence thereis an advantage in that the phase component of a signal identificationclock for the identifying circuit can be adjusted accurately so that theaccuracy of the signal identifying process in the identifying circuitcan be drastically improved.

Furthermore, according to the present invention, the clock regeneratingcircuit arranged in a receiving unit of multiplex radio equipment, thereceiving unit including an identifying circuit for identifying a signalat a predetermined identification level, the signal being obtained bydemodulating a multilevel orthogonal modulating signal and an equalizingcircuit for subjecting the demodulated signal to an equalizing process,the clock regenerating circuit regenerating a signal identificationclock for the identifying circuit and then supplying the signalidentification clock to the identifying circuit; , is characterized by aclock phase detecting unit for detecting a phase component of the signalidentification clock based on inut/output input/output signals of theequalizing circuit; , a loop filter unit for integrating the output fromthe clock phase detecting unit; , and an oscillating unit for producinga signal identification clock for the identifying circuit to theidentifying circuit, in response to as a control input the output fromthe loop filter unit.

In the clock regenerating circuit arranged in the receiving unit of themultiplex radio equipment according to the present invention, the clockphase detecting unit detects the phase component of a signalidentification clock based on the input/output signals of the equalizingcircuit; the loop filter unit integrates the resultant phase component;and the oscillating unit receives the output as a control input from theloop filter unit. Thus, the adjusted phase component of a signalidentification clock for the identifying circuit can be supplied to theidentifying circuit. Hence there is an advantage in that thevery-simplified configuration can greatly improve the signal identifyingprocess performance by the identifying circuit.

Moreover, according to the present invention, the clock phase detectingcircuit arranged in a receiving unit of multiplex radio equipment, ischaracterized by an identifying circuit for identifying a signal at apredetermined identification level, the signal being obtained bydemodulating a multilevel orthogonal modulated signal; a clockregenerating circuit for regenerating a signal identification clock forthe identifying circuit to supply the clock to said identifying circuit;and a clock phase detecting unit for detecting a phase component of thesignal identification clock based on clock phase difference informationsupplied to the identifying circuit and signal error differentialinformation obtained by the identifying circuit and then supplying theresultant phase component to the clock regenerating circuit.

In the clock regenerating circuit arranged in the receiving unit of themultiplex radio equipment according to the present invention, the clockphase detecting unit detects the phase component of a signalidentification clock based on the clock phase difference informationsupplied to the identifying circuit and the signal error differentialinformation obtained by the identifying circuit and then supplies it tothe clock regenerating circuit. Hence, the very-simplified configurationcan greatly improve the accuracy of the signal identification clockregenerating process in the clock regenerating circuit, thus greatlyimproving the accuracy of the signal identifying process in theidentifying circuit.

Furthermore, according to the present invention, the clock regeneratingcircuit arranged in a receiving unit of multiplex radio equipment, thereceiving unit having an identifying circuit that identifies a signalobtained by demodulating a multilevel orthogonal modulated signal at apredetermined identification level, the clock regenerating circuitregenerating a signal identification clock for the identifying circuitto supply the clock to said identifying circuit, is characterized by aclock regenerating unit for regenerating the signal identification clockbased on a signal before the multilevel orthogonal modulated signal isdetected; a phase adjusting unit for adjusting the phase of a clock sentfrom the clock regenerating unit and supplying the resultant clock tothe identifying circuit; and a clock phase detecting unit for detectinga phase component of the signal identification clock based on clockphase difference information supplied to the identifying circuit andsignal error differential information obtained by the identifyingcircuit and then supplying the resultant phase component to the clockregenerating circuit.

In the clock regenerating circuit arranged in the receiving unit inmultiplex radio equipment according to the present invention, when thephase adjusting unit adjusts the phase of a clock from the clockregenerating unit, the clock phase detecting unit can supply the phasecomponent of a signal identification clock detected based on the clockphase difference information supplied to the identifying circuit and thesignal error differential information, to the clock regeneratingcircuit. Hence even if the equalizing circuit that performs anequalizing process of a demodulated signal is not arranged, thevery-simplified configuration can improve the accuracy of a signalidentification clock regenerated in the clock regenerating circuit.

According to the present invention, the clock regenerating circuitarranged in a receiving unit of multiplex radio equipment, the receivingunit including an identifying circuit for identifying a signal at apredetermined identification level, the signal being obtained bydemodulating a multilevel orthogonal modulated signal, the clockregenerating circuit regenerating a signal identification clock for theidentifying circuit and then supplying the signal identification clockto the identifying circuit; , is characterized by a clock phasedetecting unit for detecting a phase component of the signalidentification clock based on clock phase difference informationsupplied to the identifying circuit and signal error differentialinformation obtained by the identifying circuit which supplies it to theclock regenerating circuit; , a loop filter unit for integrating theoutput from the clock phase detecting unit; , and an oscillating circuitfor producing a signal identification clock for the identifying circuitto the identifying circuit, in response to the output as a control inputfrom the loop filter circuit.

In the clock regenerating circuit arranged in the receiving unit ofmultiplex radio equipment according to the present invention, the clockphase detecting unit detects the phase component of a signalidentification clock for the identifying circuit, based on the clockphase difference information supplied to the identifying circuit and thesignal error differential information obtained by the identifyingcircuit, and then supplies it to the clock regenerating circuit. Hence,even if the equalizing circuit that performs an equalizing process of ademodulated signal is not arranged, the very-simplified configurationcan greatly improve the accuracy of a signal identification clockregenerated in the clock regenerating circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the first aspect of the presentinvention;

FIG. 2 is a block diagram showing the second aspect of the presentinvention;

FIG. 3 is a block diagram showing the third aspect of the presentinvention;

FIG. 4 is a block diagram showing the fourth aspect of the presentinvention;

FIG. 5 is a block diagram showing the fifth aspect of the presentinvention;

FIG. 6 is a block diagram showing the sixth aspect of the presentinvention;

FIG. 7 is a block diagram showing the configuration of each of a clockphase detecting circuit and a clock regenerating circuit arranged inmultiplex radio equipment according to the first embodiment of thepresent embodiment;

FIG. 8 is a block diagram showing the configuration of a phase componentdetecting unit according to the first embodiment of the presentembodiment;

FIG. 9 is a block diagram illustrating the detail configuration of eachof a clock regenerating circuit and the peripheral circuits according tothe first embodiment of the present invention;

FIG. 10 is a diagram used for explaining the operation of a clockregenerating circuit according to the first embodiment;

FIG. 11 is a block diagram illustrating another configuration of a phasecomponent detecting unit according to the first embodiment;

FIG. 12 is a block diagram illustrating another configuration of a clockregenerating circuit according to the first embodiment;

FIG. 13 is a block diagram illustrating a clock regenerating circuit andthe peripheral circuits according to the first embodiment;

FIG. 14 is a block diagram illustrating a phase component detecting unitaccording to the first embodiment;

FIG. 15 is a block diagram illustrating the detail configuration of eachof a clock regenerating circuit and the peripheral circuits according tothe first embodiment;

FIG. 16 is a diagram used for explaining the operation of a clockregenerating circuit according to the first embodiment;

FIG. 17 is a block diagram illustrating another configuration of a phasecomponent detecting unit according to the first embodiment;

FIG. 18 is a block diagram showing the detail configuration of a clockregenerating circuit and the peripheral circuits according to the firstembodiment;

FIGS. 19(a) to 19(c) are diagrams each used for explaining the operationof a clock regenerating circuit according to the first embodiment;

FIG. 20 is a diagram used for explaining the operation of a clockregenerating circuit according to the first embodiment;

FIG. 21 is a block diagram showing another configuration of a phasecomponent detecting unit according to the first embodiment;

FIG. 22 is a block diagram showing the detail configuration of a clockregenerating circuit and the peripheral circuits according to the firstembodiment;

FIG. 23 is a block diagram showing another configuration of a phasecomponent detecting unit according to the first embodiment;

FIG. 24 is a block diagram showing the detail configuration each of aclock regenerating circuit and the peripheral circuits according to thefirst embodiment;

FIG. 25 is a diagram showing an example of data used in a phasecomponent detecting unit according to the first embodiment;

FIG. 26 is a block diagram showing another configuration of a clockregenerating circuit according to the first embodiment;

FIG. 27 is a block diagram showing the detail configuration of each of aclock regenerating circuit and the peripheral circuits according to thefirst embodiment;

FIG. 28 is a block diagram showing the configuration of each of a clockphase detecting circuit and a clock regenerating circuit according tothe second embodiment of the present invention;

FIG. 29 is a block diagram showing the detail configuration of a clockregenerating circuit and the peripheral circuits according to the secondembodiment;

FIG. 30 is a block diagram illustrating the detail configuration of eachof a clock regenerating circuit and the peripheral circuits according tothe second embodiment;

FIG. 31 is a block diagram illustrating the detail configuration of aclock regenerating circuit and the peripheral circuits according to thesecond embodiment;

FIG. 32 is a block diagram showing another configuration of a clockregenerating circuit according to the second embodiment;

FIG. 33 is a block diagram showing the detail configuration of each of aclock regenerating circuit and the peripheral circuits according to thesecond embodiment;

FIG. 34 is a block diagram showing another configuration of a clockregenerating circuit according to the second embodiment;

FIG. 35 is a block diagram showing the detail configuration of each of aclock regenerating circuit and the peripheral circuits according to thesecond embodiment;

FIG. 36 is a block diagram showing another configuration of a composingunit arranged in a clock regenerating circuit according to the secondembodiment;

FIG. 37 is a block diagram showing another configuration of a clockregenerating circuit according to the second embodiment;

FIG. 38 is a block diagram showing the detail configuration of each of aclock regenerating circuit and the peripheral circuits according to thesecond embodiment;

FIG. 39 is a block diagram showing another configuration of a clockregenerating circuit according to the second embodiment;

FIG. 40 is a block diagram showing the detail configuration of each of aclock regenerating circuit and the peripheral circuits according to thesecond embodiment;

FIG. 41 is a block diagram showing another configuration of a clockregenerating circuit according to the second embodiment;

FIG. 42 is a block diagram showing the detail configuration of each of aclock regenerating circuit and the peripheral circuits according to thesecond embodiment;

FIG. 43 is a block diagram showing the configuration of each of a clockphase detecting circuit and a clock regenerating circuit according tothe third embodiment of the present invention;

FIG. 44 is a block diagram showing the detail configuration of each of aclock regenerating circuit and the peripheral circuits according to thethird embodiment;

FIG. 45 is a diagram used for explaining the operation of a clockregenerating circuit according to the third embodiment;

FIG. 46 is a diagram used for explaining the operation of a clockregenerating circuit according to the third embodiment;

FIG. 47 is a block diagram showing another configuration of a clockregenerating circuit according to the third embodiment;

FIG. 48 is a block diagram showing the detail configuration of each of aclock regenerating circuit and the peripheral circuits according to thethird embodiment;

FIG. 49 is a block diagram showing another configuration of a clockregenerating circuit according to the third embodiment;

FIG. 50 is a block diagram showing the detail configuration of each of aclock regenerating circuit and the peripheral circuits according to thethird embodiment;

FIG. 51 is a block diagram showing the configuration of each of a clockphase detecting circuit and a clock regenerating circuit according tothe fourth embodiment of the present invention;

FIG. 52 is a block diagram showing the detail configuration of each of aclock regenerating circuit and the peripheral circuits according to thefourth embodiment;

FIG. 53 is a block diagram showing the detail configuration of each of aclock regenerating circuit and the peripheral circuits according to thefourth embodiment;

FIG. 54 is a block diagram showing the detail configuration of each of aclock regenerating circuit and the peripheral circuits according to thefourth embodiment;

FIG. 55 is a block diagram showing another configuration of a clockregenerating circuit according to the fourth embodiment;

FIG. 56 is a block diagram showing another configuration of a clockregenerating circuit according to the fourth embodiment;

FIG. 57 is a block diagram showing another configuration of a clockregenerating circuit according to the fourth embodiment;

FIG. 58 is a block diagram showing another configuration of a clockregenerating circuit according to the fourth embodiment;

FIG. 59 is a block diagram showing the detail configuration of each of aclock regenerating circuit and the peripheral circuits according to thefourth embodiment;

FIG. 60 is a block diagram showing the configuration of a clockregenerating circuit arranged in the receiving unit of general multiplexradio equipment; and

FIG. 61 is a block diagram showing the configuration of a clockregenerating circuit arranged in the receiving unit of general multiplexradio equipment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(a) Aspect of the Invention:

By referring to the attached drawings, explanation will be made as foran aspect of the present invention.

FIG. 1 is a block diagram showing an aspect of the present invention.Referring to FIG. 1, numeral 1A represents a clock phase detectingcircuit. The clock phase detecting circuit 1A is used in the receivingunit of multiplex radio equipment including an identifying circuit 11that identifies a signal obtained by demodulating a multilevelorthogonal modulated signal at a predetermined identification level, aclock regenerating circuit 12 that regenerates a signal identificationclock for the identifying circuit 11 and then sends it to theidentifying circuit 11, and an equalizing circuit 13 that subjects asignal obtained by demodulating the multilevel orthogonal modulatedsignal to an equalizing process.

As shown in FIG. 1, the clock phase detecting circuit 1A includes aclock phase detecting unit 14A. The clock phase detecting unit 14Adetects the phase component of a signal identification clock based oninput/output signals of the equalizing circuit 13 and then supplies itto the clock regenerating circuit 12.

In the clock phase detecting circuit 1A arranged in the receiving unitof multiplex radio equipment according to the present invention, whenthe identifying circuit 11 identifies a demodulated signal obtained bydemodulating a multilevel orthogonal modulation signal at apredetermined identifying level, the clock regenerating circuit 12regenerates a signal identification clock for the identifying circuit 11and supplies it to the identifying circuit 11. At the time, the clockphase detecting unit 14A detects the phase component of a signalidentification clock in response to the input signal and the outputsignal of the equalizing circuit 13 that subjects a signal obtained bydemodulating a multilevel orthogonal modulated signal to an equalizingprocess and then supplies the phase component to the clock regeneratingcircuit 12.

According to the clock phase detecting circuit 1A as described above,there is an advantage in that the phase component of a signalidentification clock can be adjusted very accurately so that theperformance of the multiplex radio equipment can be greatly improved.

In concrete, the clock phase detecting unit 14A consists of an errordetecting unit that detects an error between the input signal and theoutput signal of the equalizing circuit 13, a signal inclinationdetecting unit that detects the inclination of a demodulated signal, anda clock phase calculating unit that calculates the output of the errordetecting unit and the output of the signal inclination detecting unitand then detects the phase component of a signal identification clock.

In the clock phase component detecting unit 14A, the error detectingunit detects the error between the input signal and the output signal ofthe equalizing circuit 13, and the signal inclination detecting unitdetects the inclination of a demodulated signal, and the clock phasecalculating unit calculates the outputs of the error detecting unit andthe signal inclination detecting unit. Thus the phase component of asignal identification clock is detected.

Hence the phase component of a signal identification clock can becertainly detected.

The clock phase detecting unit 14A may include a specific signal judgingunit that judges whether a specific signal exists and a gating unit thatproduces the phase component of a signal identification clock obtainedby the clock phase calculating unit when the specific signal judgingunit judges that a specific signal exists, in addition to the errordetecting unit, the signal inclination detecting unit, and the clockphase calculating unit.

In this case, the specific signal judging unit judges whether a receivedsignal is a specific signal. If it is judged that the received signal isa specific signal, the gating unit produces the phase component of asignal identification clock obtained by the phase calculating unit.

In the clock phase detecting unit 14A, only when the specific signaljudging unit judges that the received signal is a specific signal withgood signal quality, the gating unit can issue the phase component of asignal identification clock obtained by the clock phase calculatingunit. Hence the accuracy of the phase component of a signalidentification clock can be improved.

The signal inclination detecting unit consists of a delaying unit thatdelays the output from the identifying circuit 11 and a comparing unitthat compares the output from the identifying circuit 11 with the outputfrom the delaying unit and then detects the inclination of thedemodulated signal.

Hence the inclination of a demodulated signal which is needed in acalculation process of the phase component of a signal identificationclock can be surely obtained.

Where the identifying circuit 11 described above is used for ahigh-speed clock operation, the signal inclination detecting unitconsists of a delaying unit that calculates with high-speed clocks anddelays the output of the identifying circuit 11, a latch unit that holdsthe output of the identifying circuit 11 and the output of the delayingunit with clocks slower than the high-speed clocks, and a comparing unitthat compares the output of the identifying circuit with the output ofthe delaying unit each held in the latch unit and then detects theinclination of the demodulated signal.

In order to detect the inclination of a demodulated signal by the signalinclination detecting unit, the delaying unit calculates with high-speedclocks to delay the output from the identifying circuit 11, the latchunit holds the output of the identifying circuit 11 and the output ofthe delay unit with clocks slower than the high-speed clocks, and thecomparing unit compares the output of the identifying circuit 11 withthe output of the delaying unit each held in the latch unit.

Therefore, the sensitivity of detecting the inclination of a demodulatedsignal can be improved and the phase component of a signalidentification clock can be obtained with higher accuracy.

Moreover, the identifying circuit 11 is formed of plural identifyingunits corresponding to the number of plural demodulated signals obtainedby demodulating a multilevel orthogonal modulated signal. Clocks withdifferent predetermined phase shift may be supplied between theidentifying units. The signal inclination detecting unit includes acomparing unit that compares the outputs of the identifying units andthen detects the inclination of the demodulated signal.

In this case, the comparing unit in the signal inclination detectingunit compares the output of the identifying units to detect theinclination of the demodulated signal.

Hence, the phase component of a signal identification clock can beobtained with higher accuracy in the simple configuration, without usingthe identifying unit operated with high-speed clocks.

The clock phase calculating unit, in concrete, may be formed as amultiplying unit that subjects the output of the error detecting unitand the output of the signal inclination detecting unit to a multiplyingcalculation, or as an exclusive OR calculation unit that performs anexclusive OR calculation process.

The phase component of a signal identification clock output from theclock phase calculating unit can be obtained by subjecting the output ofthe error detecting unit and the output of the signal inclinationdetecting unit to a multiplying calculation by means of the multiplyingunit, or by performing an exclusive OR calculation by means of theexclusive OR operation unit.

Hence, the phase component detecting circuit can be realized very easilyand in a simplified configuration.

Furthermore, the specific signal judging unit includes plural signaljudging units that judge plural kinds of specific signals. A selectionunit that selects decision results sent from plural signal judging unitsis arranged between the specific signal judging unit and the gatingunit.

In this case, the selecting unit can selectively output a specific oneamong decision results from plural signal judging units.

Since the decision results from plural specific signal judging units canbe selectively output, provided that it is judged that a specific signalhas a good signal quality, the phase component of a signalidentification clock output out of the gating unit can be furtherimproved in accuracy.

FIG. 2 is a block diagram showing the second aspect of the presentinvention. Referring to FIG. 2, numeral 2A represents a clockregenerating circuit. The clock regenerating circuit 2A is arranged inthe receiving unit of multiplex radio equipment including an identifyingcircuit 11 that identifies a signal obtained by demodulating amultilevel orthogonal modulated signal at a predetermined identificationlevel and an equalizing circuit that subjects a demodulated signalobtained by demodulating a multilevel orthogonal modulation signal to anequalizing process. The clock regenerating circuit 2A regenerates asignal identification clock for the identification circuit 11 andsupplies it to the identifying circuit 11.

The clock regenerating circuit 2A includes a clock regenerating unit 15,a phase adjusting unit 16, and a clock phase detecting unit 14A.

The clock regenerating unit 15 regenerates a signal identification clockfrom a multilevel orthogonal modulated signal to be detected. The phaseadjusting unit 16 adjusts the phase of a clock from the clockregenerating unit 15 to supply to the identifying circuit 11. The clockphase detecting unit 14A detects the phase component of a signalidentification clock based on the input and output signals of theequalizing circuit 13 and supplies the resultant component as a phaseadjustment control signal to the phase adjusting unit 16.

As shown in FIG. 2, the clock regenerating circuit 2A regenerates asignal identification clock for the identifying circuit 11 to theidentifying circuit 11. In concrete, the clock regenerating unit 15regenerates a signal identification clock from a multilevel orthogonalmodulation signal to be detected. The phase adjusting unit 16 adjuststhe phase of a clock from the clock regenerating unit 15 and thensupplies to the identifying circuit 11. The phase adjustment of thephase adjusting unit 16 is performed with a phase adjustment controlsignal which is obtained by the clock phase detecting unit 14A thatdetects the phase component of a signal identification clock based onthe input and output signals of the equalizing circuit 13.

The clock regenerating circuit 2A has an advantage in that the phasecomponent of a signal identification clock for the identifying circuit11 can be adjusted accurately so that the accuracy of the signalidentification process in the identifying circuit 11 can be greatlyimproved.

An averaging unit may be arranged between the clock phase detecting unit14A and the phase adjusting unit 16 to average the output from the clockphase detecting unit 14A, thus averaging the output from the clock phasedetecting unit 14A.

Hence, the phase adjusting control signal can be obtained with moreaccuracy.

In the clock regenerating circuit 2A, the identifying circuit 11 may beformed of plural identifying units corresponding to the number of pluralsignals obtained by demodulating the multilevel orthogonal modulatedsignal. The clock regenerating unit 15, the phase adjusting unit 16, andthe clock phase detecting unit 14A may be used in common to pluralidentifying units.

In this case, the phase component of a clock identification clock foreach of the plural identifying units is detected by the clock phasedetecting unit 14A used in common to the plural identifying units. Thephase component is supplied as a phase adjustment control signal for asignal identification clock regenerated by the clock regenerating unit15 to the phase adjusting unit 16 shared by the identifying units 15.

Hence, in the receiving unit of multiplex radio equipment thatdemodulates a multilevel orthogonal modulated signal to obtain pluralsignals, the phase component of a signal identification clock can bedetected and adjusted very easily.

In the clock regenerating circuit 2A, the identifying circuit 11 may beformed of plural identifying units corresponding to the number of pluralsignals obtained by demodulating a multilevel orthogonal modulationsignal. An averaging unit is arranged between the clock phase detectingunit 14A and the phase adjusting unit 16 to average the output from theclock phase detecting unit 14A. The clock regenerating unit 15, thephase adjusting unit 16, the averaging unit, and the clock phasedetecting unit 14A may be used in common to the plural identifyingunits.

In this case, the clock phase detecting unit 14A used in common to theplural identifying units detects the phase component of a signalidentification clock for each of plural identifying units. The averagingunit performs an averaging process for the detected phase component. Theaveraged phase component is supplied as a phase adjustment and controlsignal for a signal identification clock regenerated by the clockregenerating unit 15 to the phase adjusting unit 16 used in common bythe plural identifying units.

Hence, in the receiving unit of multiplex radio equipment in whichplural demodulated signals are obtained, the phase component of a signalidentification clock can be detected and adjusted very easily. In thiscase, since the averaging unit can average the output (phase adjustmentand control signal) from the clock phase detecting unit 14A, the phaseadjustment and control signal can be obtained with higher accuracy.

In the clock regenerating circuit 2A, the identifying circuit 11consists of plural identifying units corresponding to plural signalsobtained by demodulating multilevel orthogonal modulation signal. Theclock regenerating unit 15 is used in common to the plural identifyingunits. Plural phase adjusting units 16 and plural clock phase detectingunits 14A may be arranged corresponding to the identifying units.

In this case, the phase components of signal identification clocks forthe plural identifying units are respectively detected by the clockphase detecting units 14A arranged corresponding to the identifyingunits. Each phase component is supplied as a phase adjustment andcontrol signal for a signal identification clock regenerated by theclock regenerating unit 15 to each of the phase adjusting units 16.

Hence, the clock phase detecting unit 14A corresponding to eachidentifying unit can detect the phase component of a signalidentification clock for each of plural identifying units. Each phaseadjusting unit 16 can adjust the phase component to supply to thecorresponding identifying unit. Thus the accuracy of the signalidentifying process in each identifying unit can be further improved.

In the clock regenerating circuit 2A, the identifying circuit 11 isformed of plural identifying units corresponding to the number of pluralsignals obtained by demodulating a multilevel orthogonal modulatedsignal. An averaging unit may be arranged between the clock phasedetecting unit 14A and the phase adjusting unit 16 to average the outputfrom and clock phase detecting unit 14A. The clock regenerating unit 15is shared with the identifying units. Plural phase adjusting units 16,plural averaging units, and plural clock phase detecting units 14A maybe arranged corresponding to the identifying units.

In this case, the phase components of signal identification clocks forplural identifying units are respectively detected by the clock phasedetecting units 14A arranged corresponding to the identifying units.Each of the averaging units averages each of the phase components andthen supplies the resultant phase component as phase adjustment andcontrol signals for the signal identifying clocks regenerated by theclock regenerating unit 15 to each of the phase adjusting units 16.

In this case, the signal identification clock for each of pluralidentifying units can be obtained from the corresponding clock phasedetecting unit 14A. Each of the averaging units can average a phaseadjustment and control signal for the phase adjusting unit 16 being theoutput from the clock phase detecting unit 14A. Hence the accuracy of asignal identification process in each identifying unit can be furtherimproved.

The clock regenerating circuit 2A may include a selecting unit thatselectively outputs the output of the clock phase detecting unit 14A andthe output of the test signal generating unit, in addition to a testsignal generating unit that generates a test signal. Thus the output ofthe selecting unit is supplied as an input to the phase adjusting unit16.

In the clock regenerating circuit 2A, the identifying circuit 11 may beformed of plural identifying units corresponding to the number of pluralsignals obtained by demodulating the multilevel orthogonal modulatedsignal. The clock regenerating unit 15, the phase adjusting unit 16, andthe clock phase detecting unit 14 14A may be used in common to pluralidentifying units.

The signal identification clock for the identifying circuit can betested and regenerated very easily by testing a phase adjustment processin the phase adjusting unit. This feature leads to improving theperformance of the multiplex radio equipment.

FIG. 3 is a block diagram illustrating the third aspect of the presentinvention. Referring to FIG. 3, numeral 2B represents a clockregenerating circuit. The clock regenerating circuit 2B is arranged inthe receiving unit of multiplex radio equipment including an identifyingcircuit 11 that identifies a signal obtained by demodulating amultilevel orthogonal modulated signal at a predetermined identificationlevel, and an equalizing circuit that subjects the signal obtained bydemodulating the multiplex orthogonal modulation signal to an equalizingprocess. A signal identification clock for the identifying circuit 11 isregenerated to supply to the identifying circuit 11.

The clock regenerating circuit 2B, as shown in FIG. 3, includes a clockphase detecting unit 14A, a loop filter unit 17, and an oscillating unit18.

In this case, the clock phase detecting unit 14A detects the phasecomponent of a signal identification clock based on the input signal andthe output signal of the equalizing circuit 13. The loop filter unit 17integrates the output of the clock phase detecting unit 14A. Theoscillating unit 18 receives as a control input the output of the loopfilter unit 17 and then outputs a signal identification clock for theidentifying unit 11 to the identifying circuit 11.

In the clock regenerating circuit 2B shown in FIG. 3, the clock phasedetecting unit 14A detects the phase component of a signalidentification clock based on the input signal and the output signal ofthe equalizing circuit 13 and the loop filter unit 17 integrates theoutput of the clock phase detecting unit 14A. The oscillating unit 18receives as a control input the output from the loop filter unit 17 andthen outputs a signal identification clock for the identifying unit 11to the identifying circuit 11.

According to the clock regenerating circuit 2B, there is an advantage inthat the simplified configuration allows the identifying circuit 11 toimprove greatly the performance of the signal identification process.

In the clock regenerating circuit 2B, the identifying circuit 11 may beformed of plural identifying units corresponding to the number of pluralsignals obtained by demodulating a multilevel orthogonal modulatedsignal. The clock phase detecting unit 14A, the loop filter unit 17, andthe oscillating unit 18 are used in common to the identifying units.

In such a case, the clock phase detecting unit 14A shared by theidentifying units detects the phase component of a signal identificationclock for each of plural identifying units. Then the loop filter unit 17integrates the phase component to supply the result as a control inputto the oscillating unit 18.

Consequently, in the receiving unit of multiplex radio equipment whichdemodulates a multilevel orthogonal modulation signal to obtain pluralsignals, the phase component of a signal identification clock can beadjusted automatically, accurately and very easily so that the accuracyof a signal identifying process in each identifying unit can beimproved.

In the clock regenerating circuit 2B, the identifying circuit 11 may beformed of plural identifying units corresponding to the number of pluralsignals obtained by demodulating a multilevel orthogonal modulationsignal. Plural clock phase detecting units 14A are arrangedcorresponding to the identifying units. The loop filter unit 17 and theoscillating unit 18 are used in common to the identifying units. Acomposing unit may be arranged to compose the output of each of theclock phase detecting units 14A. The output of the composing unit issupplied as an input to the loop filter unit 17.

In this case, the composing unit composes the outputs (the phasecomponents of signal identification clocks) of the plural clock phasedetecting units 14A arranged corresponding to the identifying units andthen supplies them as an input to the loop filter unit 17.

Hence, the more-simplified configuration can adjust accurately the phasecomponents of signal identification clocks supplied from the oscillatingunit 18, thus improving greatly the accuracy of the signal identifyingprocess in each identifying unit.

Furthermore, in the clock regenerating circuit 2B, the identifyingcircuit 11 may be formed of plural identifying units corresponding tothe number of plural signals obtained by demodulating a multilevelorthogonal modulation signal. Plural clock phase detecting units 14A andplural loop filter units 17 are arranged corresponding to theidentifying units. The oscillating unit 18 is used in common to eachidentifying unit. A part of the plural identifying units are connectedto the oscillating unit 18 via the phase adjusting unit to supply as acontrol input the outut of the loop filter unit 17 to the oscillatingunit 18 or the phase adjusting unit.

In this case, the loop filter unit 17 supplies its output (a signalidentification clock phase component) as a control input to theoscillating unit 18 or the phase adjusting unit.

The phase components of signal identification clocks for the identifyingunits can be detected respectively by the corresponding clock phasedetecting units 14A and then supplied as a control input to theoscillating unit 18 or the phase adjusting unit. Hence the phasecomponent of a signal identification clock can be adjusted respectivelyby the oscillating unit 18 or the phase adjusting unit to supply thesignal identification clock to each identifying unit. This featureallows each identifying unit to improve greatly the accuracy of thesignal identifying process.

In the clock regenerating circuit 2B, the identifying circuit 11 may beformed of plural identifying units corresponding to the number ofsignals obtained by demodulating a multilevel orthogonal modulationsignal. A second clock phase detecting unit is arranged to detect thephase component of a signal identification clock in a manner differentfrom that in the clock phase detecting unit 14A. The loop filter unit 17and the oscillating unit 18 are arranged in common to each identifyingunit. A corresponding unit is arranged to compose the output of theclock phase detecting unit 14A with the output of the second clock phasedetecting unit. The output of the composing unit is supplied as an inputto the loop filter unit 17.

In this case, the output (the phase component of a signal identificationclock) from the composing unit is supplied as an input to the loopfilter unit 17.

As described above, the composing unit composes the phase component ofeach signal identification clock detected by the clock phase componentdetecting unit 14A with phase component of each signal identificationclock for each identifying unit detected in a different method to supplyas an input the resultant phase component to the loop filter unit 17.Hence the phase component of a signal identification clock can beadjusted more accurately, whereby the accuracy of the signalidentification process in each identifying unit can be improved more.

Instead of the above-mentioned composing unit, a selecting unit, whichoutputs selectively the output of the clock phase detecting unit 14A andthe output of the second clock phase detecting unit, may be arranged toinput the output to the loop filter unit 17. In this case, the output ofthe selecting unit is supplied to the loop filter unit 17.

In this case, the accuracy of the signal identifying process in eachidentifying unit can be more improved by adjusting accurately the phasecomponent of a signal identification clock.

The clock regenerating circuit 2B may include a test signal generatingunit that generates a test signal as well as a selecting unit thatselects the output of the clock phase detecting unit 14A or the testsignal generating unit to supply it to the loop filter unit 17.

Thus in the clock regenerating circuit 2B, the test signal generatingunit generates a test signal and the selecting unit selectively outputsthe output of the clock phase detecting unit 14A and the output of thetest signal generating unit. Hence the output of the selecting unit canbe supplied as an input to the loop filter unit 17.

Hence the signal identification clock for the identifying circuit 11 canbe tested and regenerated very easily.

FIG. 4 is a block diagram illustrating the fourth aspect of the presentinvention. Referring to FIG. 4, numeral 1B represents a clock phasedetecting circuit. The clock phase detecting circuit 1B is used in thereceiving unit of multiplex radio equipment including an identifyingcircuit 11 that identifies a signal obtained by demodulating amultilevel orthogonal modulated signal at a predetermined identificationlevel, and a clock regenerating circuit 12 that regenerates a signalidentification clock for the identifying circuit 11 to supply theresultant to the identifying circuit 11.

As shown in FIG. 4, the clock phase detecting circuit 1B includes aclock phase detecting unit 14B. The clock phase detecting unit 14Bdetects the phase component of a signal identification clock, based onclock phase difference information supplied to the identifying circuit11 and signal error differential information obtained by the identifyingcircuit 11, and then supplies it to the clock regenerating circuit 12.

In the clock phase detecting circuit 1B shown in FIG. 4, the clock phasedetecting unit 14B detects the phase component of a signalidentification clock based on the clock phase difference informationsupplied to the identifying circuit 11 and the signal error differentialinformation obtained by the identifying circuit 11, and then suppliesthe same to the clock regenerating circuit 12.

According to the clock phase detecting circuit 1B arranged in thereceiving unit of multiplex radio equipment of the present invention,the simplified configuration can improve greatly the accuracy of thesignal identification clock regenerating process. Hence the accuracy ofthe signal identifying process in the identifying circuit 11 can begreatly improved.

In concrete, the clock phase detecting unit 14B consists of a clockphase difference detecting unit that detects clock phase differenceinformation supplied to the identifying circuit 11, a signal errordifferential detecting unit that detects signal error differentialinformation obtained by the identifying circuit 11, and a clock phasecalculating unit that detects the phase component of a signalidentification clock by calculating based on the output of the clockphase difference detecting unit and the output of the signal errordifferential detecting unit.

In order to detect the phase component of a signal identification clockby the clock phase detecting unit 14B, the clock phase differencedetecting unit detects the clock phase difference information suppliedto the identifying circuit 11 and the signal error differentialdetecting unit detects the signal error differential informationobtained by the identifying circuit 11. Then the clock phase calculatingunit subjects the output of the clock phase difference detecting unitand the output of the signal error differential detecting unit to acalculation process.

Hence, the simplified configuration can detect surely the phasecomponent of a signal identification clock.

Furthermore, the clock phase calculating unit is formed as a dividingunit that subjects the output of the error detecting unit and the outputof the signal inclination detecting unit to a division calculationprocess. In the division process of the clock phase operating unit, thedividing unit subjects the output of the error detecting unit and theoutput of the signal inclination detecting unit to a divisioncalculation process.

Hence the clock phase calculating unit can be realized very easily.

In this case, the clock phase calculating unit may be constituted as anexclusive OR calculating unit that subjects the output of the errordetecting unit and the output of the signal inclination detecting unitto an exclusive OR calculation process. In the operation in the clockphase calculating unit, the exclusive OR calculating unit subjects theoutput of the error detecting unit and the output of the signalinclination detecting unit to an exclusive OR calculation process.

Hence, the clock phase calculating unit can be realized readily in amore-simplified configuration.

FIG. 5 is a block diagram illustrating the fifth aspect of the presentinvention. Referring to FIG. 5, numeral 2A′ represents a clockregenerating circuit. The clock regenerating circuit 2A′ is arranged inthe receiving unit of multiplex radio equipment including an identifyingcircuit 11 that identifies a signal obtained by demodulating amultilevel orthogonal modulated signal at a predetermined identificationlevel. The clock regenerating circuit 2A′ regenerates a signalidentification clock to the identifying units for the identifyingcircuit 11.

As shown in FIG. 5, the clock regenerating circuit 2A′ includes a clockregenerating unit 15, a phase adjusting unit 16, and a clock phasedetecting unit 14B.

The clock regenerating unit 15 regenerates a signal identification clockfrom a multilevel orthogonal modulated signal to be detected. The phaseadjusting unit 16 adjusts the phase of a clock from the clockregenerating unit 15 to supply to the identifying circuit 11. The clockphase detecting unit 14B detects the phase component of a signalidentification clock based on clock phase difference informationsupplied to the identifying circuit 11 and signal error differentialinformation obtained by the identifying circuit 11 to supply the phasecomponent to the clock regenerating circuit 15.

In the clock regenerating circuit 2A′ shown in FIG. 5, the clockregenerating unit 15 regenerates a signal identification clock from amultilevel orthogonal modulated signal to be detected, and the phaseadjusting unit 16 adjusts the phase of a clock from the clock generatingunit 15 to supply to the identifying circuit 11. The clock phasedetecting unit 14B detects the phase component of a signalidentification clock based on clock phase difference informationsupplied to the identifying circuit 11 and signal error differentialinformation obtained by the identifying circuit 11 to supply to theclock regenerating circuit 2A′.

Hence according to the clock regenerating circuit 2A′ arranged in thereceiving unit of multilevel radio equipment of the present invention,even if an equalizing circuit that subjects a demodulated signal to anequalizing process is not provided, the accuracy of a signalidentification clock can be improved by the very-simplifiedconfiguration.

An averaging unit may be arranged between the clock phase detecting unit14B and the phase adjusting unit 16 to average the output of the clockphase detecting unit 14B. Hence the averaging unit can average theoutput (the phase component of a signal identification clock) from theclock phase detecting unit 14B.

Hence, a signal identification clock can be regenerated with higheraccuracy.

In the clock regenerating circuit 2A′, the identifying circuit 11 may beformed of plural identifying units corresponding to the number of pluralsignals obtained by demodulating a multilevel orthogonal modulatedsignal. The clock regenerating unit 15, the phase adjusting unit 16, andthe clock phase detecting unit 14B may be arranged in common to theidentifying units.

In this case, the phase component of a signal identification clock foreach identifying unit is detected by the clock phase detecting unit 14Bshared with each identifying unit and then supplied to the phaseadjusting unit 16 as a phase adjustment and control signal for a signalidentification clock regenerated by the clock regenerating unit 15.

Hence, in the receiving unit of the multiplex radio equipment in whichplural signals are obtained by demodulating a multilevel orthogonalmodulated signal, the phase component of a signal identification clockfor each identifying unit can be adjusted accurately so that theaccuracy of a signal identifying process in each identifying unit can beimproved greatly.

Moreover, in the clock regenerating circuit 2A′, the identifying circuit11 is formed of plural identifying units corresponding to the number ofplural signals obtained by demodulating a multilevel orthogonalmodulated signal. An averaging unit that averages the output from theclock phase detecting unit 14B is arranged between the clock phasedetecting unit 14B and the phase adjusting unit 16. The clockregenerating unit 15, the phase adjusting unit 16, the averaging unit,and the clock phase detecting unit 14B are used in common to eachidentifying unit.

In this case, the clock phase detecting unit 14B shared by eachidentifying unit detects the phase component of a signal identificationclock for each identifying unit. The averaging unit shared by eachidentifying unit averages the phase component and then supplies theresultant component as a phase adjustment and control signal to adjustthe phase of a signal identification clock regenerated by the clockregenerating unit 15, to the phase adjusting unit 16.

Hence, since the averaging unit can average the phase component of asignal identification clock, it can adjust more accurately the same andthen deliver to each identifying unit. Thus it is possible to improvemore greatly the accuracy of the signal identifying process in eachidentifying unit.

In the clock regenerating circuit 2A′, the identifying circuit 11 may beformed of plural identifying units corresponding to the number of pluralsignals obtained by demodulating a multilevel orthogonal modulatedsignal. The clock regenerating unit 15 is used in common to eachidentifying unit. Plural phase adjusting units 16 and plural clock phasedetecting units 14B are arranged corresponding to the identifying units.

In this case, the clock phase detecting units 14B arranged correspondingto the identifying units detect respectively the phase components ofsignal identification clocks for the identifying units and then supplythem to the phase adjusting unit 16.

Hence, since the clock phase detecting units 14B arranged correspondingto the identifying units detect respectively the phase component of asignal identification clock and the phase adjusting units 16 can adjustthem, the signal identifying clock can be supplied with higher accuracy.

In the clock regenerating circuit 2A′, the identifying circuit 11 isformed of plural identifying units corresponding to the number of pluralsignals obtained by demodulating a multilevel orthogonal modulatedsignal. An averaging unit is arranged between the clock phase detectingunit 14B and the phase adjusting unit 16 to average the output of theclock phase detecting unit 14B. The clock regenerating unit 15 is sharedwith each identifying unit. Plural phase adjusting units 16, pluralaveraging units, and plural clock phase detecting units 14B may bearranged corresponding to the identifying units.

In this case, the clock phase detecting units 14B arranged correspondingto the identifying units detect respectively the phase components ofsignal identification clocks for the identifying units. The averagingunits arranged corresponding to the identifying units average the phasecomponents to supply to the phase adjusting units 16 as phase adjustmentand control signals of signal identification clocks regenerated by theclock regenerating unit 15.

Hence, the phase components of signal identification clocks arerespectively detected by the clock phase detecting units correspondingto the identifying units, averaged by the averaging units, and adjustedby the phase adjusting units. Hence the signal identification clocks canbe supplied with higher accuracy to the identifying units.

The clock regenerating circuit 2A′ may include a test signal generatingunit that generates a test signal as well as a selecting unit thatselectively outputs the output of the clock phase detecting unit 14B andthe output of the test signal generating unit. The output of theselecting unit may be input to the phase adjusting unit 16.

In the clock regenerating circuit 2A′, the test signal generating unitgenerates a test signal. The selecting unit selectively outputs theoutput from the clock phase detecting unit 14B and the output from thetest signal generating unit to input the selected one to the phaseadjusting unit 16.

Hence, the signal identification clock sent to the identifying circuit11 can be tested and regenerated very easily.

FIG. 6 is a block diagram showing the sixth aspect of the presentinvention. Referring to FIG. 6, numeral 2B′ represents a clockregenerating circuit. The clock regenerating circuit 2B′ is arranged inthe receiving unit of multiplex radio equipment including an identifyingcircuit 11 that identifies a signal obtained by demodulating amultilevel orthogonal demodulated signal at a predeterminedidentification level. The clock regenerating circuit 2B′ regenerates asignal identification clock for the identifying circuit 11 to theidentifying circuit 11.

As shown in FIG. 6, the clock regenerating circuit 2B′ includes a clockphase detecting unit 14B, a loop filter unit 17, and an oscillating unit18.

The clock phase detecting unit 14B detects the phase component of asignal identification clock based on clock phase difference informationsupplied to the identifying circuit 11 and signal error differentialinformation obtained by the identifying circuit 11 to supply it to theclock regenerating circuit 12B. The loop filter unit 17 integrates theoutput of the clock phase detecting unit 14B. The oscillating unit 18outputs a signal identification clock for the identifying circuit 11 tothe identifying circuit 11 in response to the output acting as a controlinput of the loop filter unit 17.

As shown in FIG. 6, in the clock regenerating circuit 2B′, the clockphase detecting unit 14B detects the phase component of the signalidentification clock based on the clock phase difference informationsupplied to the identifying circuit 11 and signal error differentialinformation obtained by the identifying circuit 11. The loop filter unit17 integrates the resultant phase component. The oscillating unit 18receives the output of the loop filter unit 17 as a control input andthen outputs a signal identification clock for the identifying circuit11 to the identifying circuit 11.

Hence, according to the clock regenerating circuit 2B′, even if anequalizing circuit that subjects a demodulated signal to an equalizingprocess is not arranged, the simplified configuration can improvegreatly the accuracy of the signal identification clock.

In the clock regenerating circuit 2B′, the identifying circuit 11 mayconsist of plural identifying units corresponding to the number ofplural signals obtained by demodulating a multilevel orthogonalmodulated signal. The clock phase detecting unit 14B, the loop filterunit 17, and the oscillating unit 18 are used in common to theidentifying units.

In this case, the phase component of a signal identification clock toeach identifying unit is detected by the clock phase detecting unit 14Bwhich is shared by the identifying units. The detected phase componentis integrated by the loop filter unit 17. The oscillating unit 18receives the result as a control input to produce signal identificationclocks.

Hence, in the receiving unit of the multiplex radio equipment whichdemodulates a multilevel orthogonal modulated signal to obtain pluralsignals, the oscillating unit 18 adjusts very easily the phase componentof a signal identification clock for each identifying unit to supply toeach identifying unit. This feature allows each identifying unit toimprove the accuracy of a signal identifying process.

In the clock regenerating circuit 2B′, the identifying circuit 11 mayconsist of plural identifying units corresponding to plural signalsobtained by demodulating a multilevel orthogonal modulation signal.Plural clock phase detecting units 14B are arranged corresponding to theplural identifying units. The loop filter unit 17 and the oscillatingunit 18 are used in common to the identifying units. A composing unit isarranged to compose the output of each clock phase detecting unit 14B.The output of the composing unit is supplied as an input to the loopfiler unit 17.

In this case, the clock phase detecting units 14B arranged correspondingto the identifying units detect respectively the phase components ofsignal identification clocks sent to the identifying units. The detectedphase components are composed by the composing unit. The loop filterunit 17 receives the result as an input.

As described above, the clock phase detecting units arrangedcorresponding to the identifying units detect respectively the phasecomponents of signal identifying clocks for each identifying unit. Thecomposing unit composes the detected phase components. Then the resultis supplied to the oscillating unit 18 via the loop filter unit 17.Hence the signal identification process accuracy in each identifyingunit can be greatly improved.

Moreover, in the clock regenerating circuit 2B′, the identifying circuit11 may be formed of plural identifying units corresponding to the numberof plural signals obtained by demodulating a multilevel orthogonalmodulation signal. Plural clock phase detecting units 14B and pluralloop filter units 17 are arranged corresponding to the identifyingunits. The oscillating unit 18 is used in common to the identifyingunits. A part of plural identifying units are connected to theoscillating unit via the phase adjusting unit. The output of each loopfilter unit 17 is supplied as a control input to the oscillating unit 18or the phase adjusting unit.

In this case, the clock phase detecting units 14B arranged correspondingto the identifying units detect respectively the phase components ofsignal identification clocks for each identifying unit. Each loop filterunit 17 integrates the detected phase component to supply as a controlinput to the oscillating unit 18 or the phase adjusting unit.

Hence, the oscillating unit 18 or the phase adjusting unit adjustsrespectively the phase component of a signal identification clock foreach identifying unit and then supplies the signal identification clockto each identifying unit. Thus each identifying unit can improve greatlythe accuracy of the signal identifying process.

In the clock regenerating circuit 2B′, the identifying circuit 11 mayconsist of plural identifying units corresponding to the number ofplural signals obtained by demodulating a multilevel orthogonalmodulated signal. The second clock phase detecting unit is arranged todetect the phase component of a signal identification clock in a methoddifferent from the clock phase detecting unit 14B′. The loop filter unit17 and the oscillating unit 18 are used in common to each identifyingunit. A composing unit is arranged to compose the output of the clockphase detecting unit 14B and the output of the second clock phasedetecting unit. The output of the composing unit is supplied as an inputto the loop filter unit 17.

In this case, the clock phase detecting unit 14B and the second clockphase detecting unit detect the phase component of a signalidentification clock for each identifying unit according to differentmethods, respectively. The composing unit composes the detected phasecomponents to supply as an input to the loop filter unit 17.

Hence, the signal identification clock can be supplied to eachidentifying unit by adjusting more accurately the phase component of asignal identification clock for each identifying unit, whereby theaccuracy of a signal identifying process in each identifying unit can bemore improved.

In this example, instead of the composing unit, a selecting unit thatoutputs selectively the output of the clock phase detecting unit 14B andthe output of the second clock phase detecting unit may be arranged tosupply the resultant output as an input to the loop filter unit 17.

In this case, the selecting unit selectively supplies the phasecomponents of signal identification clocks detected in a differentmethod by means of the clock phase detecting unit 14B and the secondclock phase detecting unit to the loop filter unit 17 as an input.

Hence, in this case, the accuracy of a signal identifying process ineach identifying unit can be greatly improved.

The clock regenerating circuit 2B′ may include a selecting unit thatselectively outputs the output of the clock phase detecting unit 14B andthe output of the test signal generating unit in addition to a testsignal generating unit that generates a test signal. The output of theselecting unit is supplied to the loop filter unit 17 as an input.

Thus in the clock regenerating circuit 2B′, the test signal generatingunit generates a test signal and the selecting unit selectively outputsthe output of the clock phase detecting unit 14B and the output of thetest signal generating unit to supply the selected one to the loopfilter unit 17.

Hence, the signal identification clock for the identifying circuit 11can be tested and regenerated very easily.

(b) First Embodiment of the Present Invention:

Next, the first embodiment according to the preset invention will beexplained below by referring to the attached drawings.

FIG. 7 is a block diagram showing the configuration of each of a clockphase detecting circuit and a clock regenerating circuit each arrangedin the receiving unit in multiplex radio equipment, according to thefirst embodiment of the present invention. Referring to FIG. 7, numeral22 represents an orthogonal detecting unit that detects an IF bandsignal (in this embodiment, it is assumed that a multiplex radioequipment on an originating side performs an orthogonal modulation suchas PSK or QAM) received by the multiplex radio equipment and obtained byperforming a frequency conversion and then obtains two kinds of baseband signals (an Ich signal and a Qch signal) being different(perpendicular to) by 90° in phase from each other; 23 and 24 representidentifying units each that identifies the output (signals obtained bydemodulating multilevel orthogonal modulated signals) from theorthogonal detecting unit 22 at a predetermined identification level; 25represents an equalizer (equalizing circuit) that subjects the output (asignal obtained by demodulating a multilevel orthogonal modulationsignal) from the identifying units 23 or 24 to an equalizing process.

In this embodiment, as shown in FIG. 9, the orthogonal detecting unit 22consists of hybrid circuits (H) 221 and 222, phase detectors 223 and224, roll-off filters 225 and 226, and a local oscillating unit 227. Theidentifying units 23 and 24 correspond respectively to two kinds(plural) of signals (an Ich signal and a Qch signal) obtained bydemodulating a multilevel orthogonal modulated signal. The identifyingunits 23 and 24 are formed of two A/D converters, respectively. Theequalizer 25 is formed of a transversal equalizer.

In the orthogonal detecting unit 22, the hybrid circuit 221 splits theinput IF signal into two signals. The two signals are outputrespectively to the phase detectors 223 and 224. At this time, the localoscillating unit 227 supplies a carrier regenerating signal synchronizedin phase with the a carrier wave to the hybrid circuit 222. The hybridcircuit 222 splits the carrier regenerating signal into two signals withphases being different by 90° from each other and then outputs themrespectively to the phase detectors 223 and 224.

As a result, the phase detectors 223 and 224 produce respectively baseband signals (an Ich signal and a Qch signal) with phases beingdifferent by 90° from each other. The A/D converter (identifying unit)23 subjects an Ich signal via the roll-off filter 225 to an A/Dconversion (signal identification) while the A/D converter (identifyingunit) 24 subjects a Qch signal via the roll-off filter 226 to an A/Dconversion (signal identification). As a result, digital demodulatedsignals different from 90° in phase from each other are obtained. Thetransversal equalizer 25 subjects the digital demodulated signals to anequalizing process.

Referring to FIG. 7, numeral 26 represents a phase component detectingunit. The clock regenerating circuit 35 being the main portion accordingto the present invention consists of the integrator 27, the phaseshifter 28, and the clock regenerating unit 29, in addition to the phasecomponent detecting unit 26. According to the present embodiment, thephase component detecting unit 26, the integrator 27, the phase shifter28, and the clock regenerating unit 29 are used in common to theidentifying units 23 and 24.

The phase component detecting unit (clock phase detecting unit(circuit)) 26 detects the phase component of a signal identificationclock (signal identification clock) in the identifying units 23 and 24based on the input and output signals (Ich signals) of the equalizer 25and then supplies it as a phase adjusting and control signal to thephase shifter 28 (to be described later). As shown in FIG. 8, the phasecomponent detecting unit 26 consists of an inclination judging unit 30,an error detecting unit 31 formed of a subtracter 311 and a clock phasecalculating unit 32 formed of a multiplier 321.

The inclination judging unit (signal inclination detecting unit) 30detects the inclination of an Ich signal (demodulated signal) (asdescribed later). In the error detecting unit 31, the subtracter 311subjects the Ich input signal and the Ich output signal of the equalizer25 to a substracting process to detect an error (hereinafter, referredto as a signal error) between the Ich input signal and the Ich outputsignal of the equalizer 25. In the clock phase calculating unit 32, themultiplier 321 subjects the output of the inclination judging unit 30and the output of the error detecting unit 31 (subtracter 311) to amultiplying process and then detects the phase component of a signalidentification (A/D conversion) clock to the identifying units (A/Dconverters) 23 and 24.

The inclination judging unit 30, as shown in FIG. 9 is formed offlip-flop (FF) circuits 301 and 302, a ROM 303, and a time adjustingunit 304. Each of the FF circuits (delaying units) 301 and 302 delays intime the output of the A/D converter 23. The ROM (comparing unit) 303compares the output from the FF circuit 301 with the output from the FFcircuit 302 to detect the inclination of the Ich signal (demodulatedsignal).

The multiplier (clock phase calculating unit 32) 321 multiplies theinclination of an Ich signal detected by the ROM 303 with the signalerror of the Ich signal obtained by subjecting the input signal and theoutput signal of the transversal equalizer 25 to a subtracting processby means of the subtracter 311 (error detecting unit 31). As a result,each of the A/D converters 23 and 24 can obtain information (phasecomponent) regarding the phase deviation of an A/D conversion (signalidentification) clock supplied as an A/D conversion operation timing.

Each of the time adjusting units 31A and 304 adjusts in time so as toagree the output from the inclination judging unit 30 with the outputfrom the error detecting unit 31 in a multiplying timing of the clockphase calculating unit 32.

The integrator (averaging unit) 27 arranged between the phase componentdetecting unit 26 and the phase shifter 28 averages the output of thephase component detecting unit 26. As shown in FIG. 9, the integrator 27is formed of a resistor (R) 271 and a capacitor (C) 272. The resistor271 and the capacitor 272 averages an A/D conversion clock phasedeviation information converted from a digital signal to an analogsignal by the D/A converter 33.

The phase shifter (phase adjusting unit) 28 adjusts the phase of an A/Dconversion clock generated by the clock regenerating unit 29 (to bedescribed later) based on the information regarding the phase deviationof an A/D conversion clock detected by the phase component detectingunit 26 and averaged by the integrator 27 and then supplies the resultto the identifying units (A/D converters) 23 and 24.

The clock regenerating unit 29 regenerates the A/D conversion clock fromthe IF signal to be detected by the orthogonal detecting unit 22 andsupplies it to the identifying units (A/D converters) 23 and 24.Generally, as shown in FIG. 9, the clock regenerating unit 29 is formedof a square detecting unit 291 which performs a square detection, loopfilters 292 and 295, a phase detector (PD) 294, an amplifier 296, and anoscillating unit 297. In this embodiment, the phase detector 294, theloop filter 295, the amplifier 296, and the oscillating unit 297 providethe so-called PLL circuit 293.

The operations of the phase component detecting unit 26 and the clockregenerating circuit 35 each being the above-mentioned main elementaccording to the present invention will be described below in detailwith reference to FIG. 9.

In the phase component detecting unit 26, each of the FF circuits 301and 302 delays part of the Ich signal (digital demodulated signal) to beequalized by the transversal equalizer 25 at intervals of e.g. time T(that is, sampled at intervals of time T), and then inputs theinformation regarding each of signal levels at three points to the ROM303. The ROM 303, for example, as shown in FIG. 10, time-sequentiallystores and compares three pieces of information regarding the signallevels at three points (−T,0,T) to detect the inclination “g” of the Ichsignal.

If the transversal equalizer 25 equalizes the Ich signal with theinclination “g” by “e”, the subtracter 311 in the error detecting unit31 subjects the Ich signal to be equalized by the transversal equalizer25 and the Ich signal after an equalizing process to a subtractingprocess, thus producing a signal error “e”.

In this case, as shown in FIG. 10, the phase of the A/D conversion clockis shifted by “Δt” from the optimum phase at which the opening portionof the eye pattern is opened maximumly. However, the phase shift “Δt” isexpressed by the following formula:Δt=g×e   (1)where “g” is the inclination of the Ich signal and “e” is a signal errorof the Ich signal. Hence the multiplier 321 in the clock phasecalculating unit 32 detects an A/D conversion clock phase shift “Δt” bymultiplying the inclination “g” of the Ich signal by the signal error“e” of the Ich signal. Then the phase shift “Δt” can be supplied to theclock regenerating circuit 35 and then regenerated as an A/D conversionclock phase adjustment and control signal in the clock regenerating unit29.

In the clock regenerating circuit 35, the IF signal to be detected bythe orthogonal detecting unit 22 is processed desirably through thesquare detecting unit 291, the filter 292, and the PLL circuit 293 sothat an A/D conversion timing signal is created to the A/D converters 23and 24. The D/A converter 33 converts the phase shift “Δt” of an A/Dconversion clock as described above from a digital signal to an analogsignal and then the integrator 27 averages the analog signal. The phaseshifter 28 receives the output of the integrator 27 as a phaseadjustment and control signal to adjust the phase shift of the A/Dconversion clock, thus sending it to the A/D converters 23 and 24.

Therefore, the A/D conversion clock to the A/D converters 23 and 24 tobe regenerated in the clock regenerating circuit 35 can be always agreedto the optimum phase at which the opening portion of the eye pattern isopened maximumly. As a result, each of the A/D converters 23 and 24 canimprove greatly the accuracy of the A/D conversion process.

As described above, the error detecting unit 31 detects the input signalto output signal error “e” of the transversal equalizer 25 while theinclination judging unit (signal inclination detecting unit) 30 detectsthe inclination “g” of the demodulated signal. Then the multiplier 321in the clock phase calculating unit 32 multiplies the output of theerror detecting unit 31 by the output of the inclination judging unit30. Thus the phase shift (phase component) “Δt” of an A/D conversionclock can be obtained, whereby the phase shift of an A/D conversionclock can be surely detected.

Furthermore, the A/D conversion clock for the A/D converters(identifying units) 23 and 24 is obtained by means of the phasecomponent detecting unit 26, the integrator 27, the phase shifter 28,and the clock regenerating unit 29 each used in common to the A/Dconverters (identifying units) 23 and 24. Hence in the receiving unit inthe multiplex radio equipment wherein two kinds of orthogonal signals(an Ich signal and a Qch signal) are obtained by demodulating amultilevel orthogonal modulation signal such as 16 QAM, the phase shiftof an A/D conversion clock can be detected and adjusted by avery-simplified configuration.

Since the integrator 27 can average the output (phase adjustment andcontrol signal) of the phase component detecting unit 26, the accuracyof the phase adjustment and control signal to the phase shifter 28 canbe increased, whereby the phase shifter 28 can perform accurately thephase adjusting process.

If the inclination “g” obtained by the inclination judging unit 30 andthe signal error “e” obtained by the error detecting unit 31 are simplyexpressed only by polarity, the clock phase calculating unit 32 (referto FIG. 8) may be formed of an EX-OR gate (exclusive OR element) 322instead of the multiplier 321, as shown in FIG. 11. Hence the moresimplified configuration can detect the phase shift (phase component) ofan A/D conversion clock.

In the clock regenerating circuit 35, the phase component detecting unit26 arranged on the Ich channel side detects the phase shift of an A/Dconversion clock from the Ich signal. However, the phase componentdetecting unit 26 may be arranged on the Qch channel side to detect thephase shift of an A/D conversion clock based on the Qch signal. In theembodiments to be described later, the phase shift of an A/D conversionclock can be detected using either the Ich signal or Qch signal.

FIGS. 12 and 13 are block diagrams each illustrating anotherconfiguration of the clock regenerating circuit 35. In the clockregenerating circuit 35A shown in FIGS. 12 and 13, the clockregenerating unit 29 is used in common to identifying units (A/Dconverters) 23 and 24. The phase shifter 28A, the integrator 27A, andthe phase component detecting unit 26A which correspond respectively tothe phase shifter 28, the integrator 27, and the phase componentdetecting unit 26, described with FIGS. 7 and 9, are arranged to theidentifying unit 23. The phase shifter 28B, the integrator 27B, and thephase component detecting unit 26B which correspond respectively to thephase shifter 28, the integrator 27, and the phase component detectingunit 26, described with FIGS. 7 and 9, are arranged to the identifyingunit 24.

Each of the phase component detecting units 26A and 26B shown in FIG. 13resembles structurally the phase component detecting unit 26A shown inFIG. 11. The clock phase calculating unit 32 is constituted as an EX-ORgate 322. The clock phase calculating unit 32 may be formed as themultiplier 321 shown in FIG. 7. In FIGS. 12 and 13, the same signs asthose shown in FIGS. 7 and 9 represent same elements.

In the clock regenerating circuit 35A having the above-mentionedconfiguration, like the configuration shown in FIGS. 7 and 9, the phasecomponent detecting unit 26A arranged corresponding to the channel (Ich)identifying unit 23 detects the phase shift of an A/D conversion clockbased on an Ich signal while the phase component detecting unit 26Barranged corresponding to the channel (Qch) identifying unit 24 detectsthe phase shift of an A/D conversion clock based on a Qch signal. Theintegrator 27 27A averages the phase shift of an A/D conversion clock tosupply as a phase adjustment and control signal for the phase shifter28A to the phase shifter 28A while the integrator 27 27B averages thephase shift of an A/ID A/D conversion clock to supply as a phaseadjustment and control signal for the phase shifter 28B to the phaseshifter 28B. As a result, the phase shifters 28A and 28B adjustindependently the phase of the A/D conversion clock regenerated in theclock regenerating unit 29 and supply it respectively to the identifyingunits 23 and 34.

Hence, compared with the clock regenerating circuit 35 shown in FIGS. 7and 9, the signal identification clocks supplied to the identifyingunits 23 and 24 can be agreed with higher accuracy the optimum timing(at which the opening portion of the eye pattern is opened maximumly).Hence the accuracy of the signal identifying process in each of theidentifying units 23 and 24 can be improved largely.

The inclination judging unit 30 in the phase component detecting unit 26(26A or 26B), as described in FIG. 10, detects the inclination “g” of anIch signal by sampling and comparing the Ich signal to be equalized bythe transversal equalizer 25 at the time T. However, the inclination ofthe Ich signal can be detected more accurately by shortening thesampling time.

For example, when a high-speed identifying unit that calculates at atwofold clock speed is used for the identifying unit 23 and the Ichsignal to be equalized by the transversal equalizer 25 is sampled at aninterval of time T/2, the inclination of a signal can be accuratelydetected merely by comparing the signal levels at two points including acurrent time “0” and a past time “−T/2”.

FIG. 14 is a block diagram illustrating the configuration of ainclination judging unit using the high speed identifying unit 23′ thatcalculates at a twofold clock speed instead of the identifying unit 23based on the above-mentioned theory. In this case, the inclinationjudging unit 30A is formed of flip-flop (FF) circuits 305 and 306 and acomparing unit 307.

The FF circuit (delaying unit) 305 calculates at a twofold clock speed(high speed) to delay the output of the identifying unit 23′ by the timeT/2. The FF circuit (latching unit) 306 latches (holds) the output ofthe identifying unit 23′ and the output of the FF circuit 305 atintervals of time T, based on the basic clock (slower than the highspeed clock) obtained by dividing the high speed clocks by means of thefrequency divider 36. The comparing unit 307 compares the output of theidentifying unit 23′ latched by the FF circuit 306 with the output ofthe FF circuit 305 and then detects the inclination of the Ich signal(demodulated signal).

In the inclination judging unit 30A having the above-mentionedconfiguration, the FF circuit 306, for example, as shown in FIG. 16,latches the current Ich signal (at the time “0”) and the past Ich signal(at the time “−T/2”) delayed by the time T/2 by the FE FF circuit 305and then outputs them to the comparing unit 307 according to the basicclocks from the frequency divider 36.

The comparing unit 307 compares the signal levels at two points of thetime “0” and the time “−T/2” to detect the inclination of the Ichsignal.

FIG. 15 is a block diagram showing the detail configuration of each ofthe clock regenerating circuit 35A and the peripheral circuits in thecase where the inclination judging unit 30A is applied instead of theinclination judging unit 30 in the phase component detecting unit 26shown in FIG. 9. In this case, a comparator (COMP) is used as thecomparing unit 307 and a flip-flop (FF) circuit with input and outputterminals loop-connected partially is used as the frequency divider 36.The time adjusting unit (τ) 308 arranged to the output side of the FFcircuit 306 adjusts the time for which the Ich signal is input to thesubtracter 311 to agree the inclination of an Ich signal to be operatedby the clock phase calculating unit 32 with the signal error in theinput timing.

In FIG. 15, an oscillating unit 297′ which generates at a frequencytwice the basic frequency (f) is used in the PLL circuit 293 to createtwo-fold speed clocks in the clock regenerating unit 29. In FIG. 15,like numerals represent like elements shown in FIG. 9.

In this case, in the phase component detecting unit 26, as shown in FIG.14, the EX-OR gate (clock phase calculating unit 32) 322 calculates theinclination of an Ich signal to be detected by the inclination judgingunit 30A just before the transversal equalizer 25 equalizes, and asignal error and then detects the phase shift of the A/D conversionclocks input to the A/D converters 23′ and 24. The signal error isobtained by subjecting the input and output signals of the transversalequalizer 25 to a subtracting process by the subtracter 311 (errordetecting unit 31).

Thereafter, like the configuration shown in FIG. 9, the D/A converter 33converts the phase shift of the A/D conversion clock from the digitalsignal into an analog signal. Then the integrator 27 averages the analogsignal and outputs as a phase adjustment and control signal to the phaseshifter 18. The phase shifter 18 adjusts automatically the phase shiftof the A/D conversion clock for the A/D converters 23′ and 24 (in thiscase, two-fold speed clock) regenerated by the clock regenerating unit29 according to the above-mentioned phase adjustment and control signalto supply to the A/D converters 23′ and 24.

As described above, according to the clock regenerating circuit 35Ashown in FIG. 15, since the signal level of the Ich signal is sampledand compared at intervals of the time “T/2” shorter than the basic clocksampling time “T”, using the two-fold high speed clocks, the inclinationof the Ich signal can be detected more accurately. Hence the phase shiftof the A/D conversion clock regenerated by the clock regenerating unit29 can be adjusted more accurately and the A/D conversion clocks withhigher accuracy can be obtained for the A/D converters 23′ and 24.

The phase component detecting unit 26 samples and compares the Ichsignals at two points including the time “−T/2” and the time “0” todetect the inclination of the Ich signal. However, when a FF circuit isused to delay additionally the output of the FF circuit 305 by the time“T/2”, the inclination of the Ich signal can be detected more accuratelyby sampling the Ich signals at three points including the time “−T/2”,the time “0”, and the time “T/2” and then by comparing the signal levelof the three Ich signals by the COMP 307.

Instead of the high speed clock identifying unit (A/D converter) 23′that calculates at the two-fold clock speed, as shown in FIG. 17, theidentifying units 23A and 23B shown in FIG. 7 or 12, and the delayingunit 37 (in this example, the inverting gate 371) can be used to supplytwo kinds of clocks different in phase by “T/2” from each otherrespectively to the identifying units 23A and 23B between theidentifying units 23A and 23B. Thus the inclination judging unit 30B canbe constituted of only the comparing unit 307 so that the Ich signal canbe sampled at intervals of the time “T/2”.

For example, when the Ich signal (data), as shown in FIG. 19(a), isinput to the identifying unit 23A, the clock pulses (1) having an “H”level at intervals of the time “T/2” is supplied to the identifying unit23A as shown in FIG. 19(b). The clock pulses (2) different in phase by“T/2” from the clock pulses input to the identifying unit 23A (or clockpulses different in phase by a predetermined amount) is supplied to theidentifying unit 23B by inverting a part of the clock pulses by theinverting gate 371 in the delaying unit 37.

When the clock turns to the “H” level, each of the identifying units 23Aand 23B outputs data. As a result, the comparing unit 307, for example,receives data at the time “0” and data at the time “T/2” to compare thetwo signal levels, thus detecting the inclination of the Ich signal(data).

FIG. 18 is a block diagram illustrating the detailed configuration ofthe peripheral circuits in the case where the circuit described withFIG. 17 is applied as the clock regenerating circuit 35B to the clockregenerating circuit 35A shown in FIG. 15. In FIG. 18, the identifyingunits 23A and 23B are constituted as A/D converters. The comparing unit307 is constituted as the comparator (COMP) 307.

The A/D converter 23B receives the A/D conversion clocks obtained bydelaying a part of the A/D conversion clocks supplied to the A/Dconverter 23A by the time “T/2” by the delaying unit 37. The COMP 307compares the signal levels of Ich signals at two points output atintervals of the time “T/2” to detect the inclination of the Ich signal.

Thereafter, the EX-OR gate (clock phase calculating unit 32) 321subjects the inclination of an Ich signal obtained as described aboveand the signal error of the Ich signal to an exclusive OR calculation.The signal error of the Ich signal is obtained by subjecting the inputsignal and the output signal of the transversal equalizer 25 to asubtracting process by the subtracter (error detecting unit 31) 311.Thus the phase shift of the A/D conversion clock to the A/D converters23A, 23B and 24 is detected.

After the integrator 27 averages the phase shift of the A/D conversionclock, the phase shifter 28 receives the result as a phase adjustmentand control signal to adjust the phase of the A/D conversion clock whichis regenerated by the clock regenerating unit 29 and supplied to the A/Dconverters 23 and 24.

As described above, according to the clock regenerating circuit 35Bwhich does not include the high-speed clock identifying unit (A/Dconverter) 23′ shown in FIGS. 14 and 15, the Ich signal can be sampledat intervals of the time “T/2” by supplying clocks different in phase bythe time “T/2” (or by a different predetermined amount in phase)respectively to the identifying units (A/D converters) 23A and 23B,without using the delaying circuit such as a flip-flop (FF) circuit.Hence, the inclination of an Ich signal can be detected more accuratelyusing the more-simplified configuration, whereby the phase shift of theA/D conversion clock can be detected more accurately.

Hence the phase shifter 28 can adjust automatically and with highaccuracy the phase shift of the A/D conversion clock for the identifyingunits (A/D converters) 23A, 23B, and 24 to be regenerated by the clockregenerating unit 29 and then supplies it to the identifying units (A/Dconverters) 23A, 23B, and 24.

In the above embodiment, the inverting gate 371 in the delaying unit 37(see FIG. 17) inverts the clock to be supplied to the identifying unit(A/D converter) 23A and then shifts the phase of the clock to besupplied to the identifying unit (A/D converter) 23B by “T/2” to samplethe Ich signal at intervals of the time “T/2”. However, the Ich signalcan be sampled at intervals of time shorter than the time “T/2” (e.g.the time “0” and the time “α”) as shown in FIG. 20, by using an elementdelaying the clock phase by the shorter time “d” than the time “T/2” inthe delaying unit 37. As a result, the inclination of the Ich signal canbe detected more accurately.

FIG. 21 is a block diagram illustrating another configuration of thephase component detecting unit (clock phase detecting circuit) 26described with FIGS. 7 and 8. The phase component detecting unit 26C,shown in FIG. 21, includes a signal judging unit 41 and a flip-flop (FF)circuit 42, in addition to the inclination judging unit 30, an errordetecting unit 31 acting as the subtracter 311, and a clock phasecalculating unit 32 acting as the multiplier 321 described with FIG. 8.

The signal judging unit (specific signal judging unit) 41 judges whetherthe signal point of the Ich signal input to the inclination judging unit30 and the error detecting unit 31 is at a specific position of theso-called eye pattern (e.g. near the middle portion of the eye pattern)and the Ich signal is in a relatively good state in signal quality (orwhether the signal point is a specific signal or not). The FF circuit(gating unit) 42 produces the phase shift (phase component) of an A/Dconversion clock (signal identifying clock) obtained by the clock phasecalculating unit 32 (multiplier 321), in response to signal notifyingthat the signal judging unit 41 judges that the signal point of the Ichsignal to be input to the inclination judging unit 30 and the errordetecting unit 31 is in a specific position of the eye pattern.

FIG. 22 is a block diagram illustrating the detail configuration of theclock regenerating circuit 35C and the peripheral circuits in the casewhere the phase component detecting unit 26C is used instead of thephase component detecting unit 26 shown in FIG. 7. As shown in FIG. 22,the inclination judging unit 30 is formed of the flip-flop (FF) circuits301 and 302 and the comparing unit (ROM) 303, corresponding to thoseshown in FIG. 9. The signal judging unit 41 is formed of a ROM 411 andan AND gate 412. Numerals 31A, 31B and 304 represent time adjustingunits (τ) each which agrees with the operational timing of each unit. InFIG. 22, like numerals and symbols represent like elements in FIG. 9.

In this case, the ROM 303 in the inclination judging unit 30 stores dataregarding the inclination of an Ich signal detected. The ROM 411 withinthe signal judging unit 41 stores as signal quality status judging datapartial data shown with the shaded portion among data formed of theso-called signal bit (D1, D2) and an error bit (D3, D4, . . . ), asshown in FIG. 25.

The phase component detecting unit 26C judges whether the signal pointof an Ich signal input to the inclination judging unit 30 and the errordetecting unit 31 is at a specific position of an eye pattern, based ondata stored in the ROM 303 in the signal judging unit 41. If the signalpoint is at the specific position, the clock phase calculating unit(multiplier 321) 32 multiplies the inclination of an Ich signal detectedby the inclination judging unit 30 by the signal error of an Ich signalobtained by the error detecting unit (subtracter 311) 31. Then the FFcircuit 42 outputs the phase shift (phase component) of the resultantA/D conversion clock.

Thereafter, the D/A converter 33 converts the phase shift of theabove-detected A/D conversion clock from a digital signal into an analogsignal. Then the integrator 27 averages the resultant analog signal andthen supplies it to the phase shifter 28 as an A/D conversion clockphase adjustment and control signal for the A/D converters 23 and 24regenerated by the clock regenerating unit 29.

As described above, according to the phase component detecting unit 26C,only when the signal point of an Ich signal input to the inclinationjudging unit 30 and the error detecting unit 31 is at a specificposition of the eye pattern, the phase shift of the A/D conversion clockdetected is supplied as a phase adjustment and control signal to thephase shifter 28. Hence the phase shift of the A/D conversion clock canbe adjusted more accurately so that the A/D conversion clock for the A/Dconverters 23 and 24 can be agreed with the phase of optimum A/Dconversion timing at which the opening of the eye pattern is opened atits maximum.

FIG. 23 is a block diagram illustrating another configuration of thephase component detecting unit 26 described with FIGS. 7 and 8. Thephase component detecting unit 26D shown in FIG. 23 includes signaljudging units 41A and 41B, a flip-flop (FF) circuit 42, and a signalquality judging unit 44, in addition to the inclination judging unit 30,the error detecting unit 31 acting as the subtracter 311, and the clockphase calculating unit 32 acting as the multiplier 321. A selecting unit43 is arranged between the signal judging units 41A and 41B and theflip-flop (FF) circuit 42.

Each of the signal judging units 41A and 41B corresponds to the signaljudging unit 41 shown in FIG. 21. However, in this case, each of thesignal judging units 41A and 41B judges whether the signal point of theIch signal input to the inclination judging unit 30 and the errordetecting unit 31 is at a different specific position of the eye pattern(or judges plural kinds of specific signals). The selecting unit 43selects the decision result issued when it is judged that the signalpoint of the Ich signal to each of the signal judging units 41A and 41Bis at a specific position, according to the control signal from thesignal quality judging unit 44 (to be described later) and then outputsit to the FF circuit 42.

When receiving the output from the selecting unit 43, the FF circuit(gating unit) 42 outputs the phase shift (phase component) of an A/Dconversion clock (signal identification clock) obtained by the clockphase calculating unit (multiplier 321) 32. The signal quality judgingunit 44 judges the signal quality status of a demodulated signal andthen supplies the decision result as a control signal for the selectingunit 43 to the selecting unit 43.

As described above, in the phase component detecting unit 26D, theselecting unit 43 can selectively output the output of the signaljudging unit 41A or 41B according to the signal quality status from thesignal quality judging unit 44. In other words, since the specificposition can be changed on the eye pattern of a signal point to bejudged according to the signal quality status of the demodulated signal,the phase shift of an A/D conversion clock can be detected accuratelywithout depending on the signal quality of an Ich signal (or a Qchsignal) used to detect the phase shift of an A/D conversion clock.

FIG. 24 is a block diagram illustrating the detailed configuration ofthe clock regenerating circuit 35D and the peripheral circuits to whichthe above-mentioned phase component detecting unit (clock phasedetecting circuit) 26D is applied. The phase component detecting unit26D, shown in FIG. 24, includes a selector (SEL) acting as the selectingunit 43 and a frame synchronizing circuit acting as the signal qualityjudging unit 44 that performs an error correction to a post equalizationsignal from the transversal equalizer 25. In FIG. 24, it should be notedthat like numerals represent like elements shown in FIG. 9.

The clock regenerating circuit 35 (or 35A) shown in FIG. 7 (or FIG. 12)may include a random pulse generating unit 47 and a selecting unit 46which produces its output to the phase shifter 28 via the integrator 27and the amplifier 45, as shown in FIG. 26.

The random pulse generating unit (test signal generating unit) 47generates random pulses to test the clock regenerating circuit 35 (or35A). In this case, the random pulse generating unit 47 generates thepulse of the middle value of a detection result in phase shift of an A/Dconversion clock of the phase component detecting unit 26 (or 26A or26B).

The selecting unit 46 outputs selectively the output of the phasecomponent detecting unit 26 (or 26A or 26B) or the output of the randompulse generating unit 47, in response to a test/normal switching signal.The integrator 27 corresponds to that described with FIG. 7 (or FIG. 12)and averages the output of the selecting unit 46. The amplifier 45amplifies the output of the integrator 27 to a desired signal level.

In concrete, the random pulse generating unit 47, as shown in FIG. 27,consists as a PN pattern generating circuit formed of four flip-flop(FF) circuits 471 to 474 and an EX-OR gate 475. The selecting unit 46 isformed as a selector (SEL). In FIG. 26 and FIG. 9 or 13, the samenumerals represent the same elements.

In such a configuration, when the SEL 46 receives an adjustment (ortest) signal to adjust (test) the clock regenerating circuit 35, itselects a random pulse (test signal) generated by the PN patterngenerating circuit 47, instead of the phase shift (phase component) ofan A/D conversion clock to the A/D converters 23 and 24 detected by thephase component detecting unit 26 shown in FIGS. 7 to 9. Then theintegrator 27 averages the random pulse and then sends the result as aphase adjustment and control signal for the phase shifter 28 to thephase shifter 28.

Hence the phase shifter 28 can test and adjust very easily the phaseshift of an A/D conversion clock to the A/D converters 23 and 24.

(c) Second Embodiment of the Present Invention:

FIG. 28 is a block diagram showing the configuration of each of theclock phase detecting circuit and the clock regenerating circuitarranged in multiplex radio equipment according to the secondembodiment. Referring to FIG. 29, numeral 22 represents an orthogonaldetecting unit that detects an IF signal obtained by subjecting it to afrequency conversion, the IF signal being received by the multiplexradio equipment similar to that shown in the first embodiment, and thenproduces two kinds of signals (an I-channel (Ich) signal and a Q-channel(Qch) signal) with phases different by 90° from each other; 23 and 24represent an identifying unit that identify the output (a signalobtained by demodulating a multilevel orthogonal modulated signal) ofthe orthogonal detecting unit 22 at a predetermined identificationlevel; and 25 represents an equalizer (equalizing circuit) that subjectsthe outputs (a signal obtained by demodulating a multilevel orthogonalmodulated signal) of the identifying units 23 and 24 to an equalizingprocess.

In this embodiment, as shown in FIG. 29, the orthogonal detecting unit22 consists of hybrid circuits (H) 221 and 222, the phase detectors 223and 224, roll-off filters 225 and 226, and a local oscillating unit 227.The identifying units 23 and 24 are formed of two A/D converterscorresponding to two kinds (plural) of signals (an Ich signal and a Qchsignal) obtained by demodulating a multilevel orthogonal modulationsignal. The equalizer 25 is formed of a transversal equalizer. Theabove-mentioned elements have been explained in detail in the firstembodiment by referring to FIG. 9. Hence the duplicate explanation willbe omitted here.

In FIG. 28, numeral 26 represents a phase component detecting unit(clock phase detecting unit (circuit)) similar to that shown in FIG. 11.In this case, as shown in FIG. 29, the phase component detecting unit 26consists of the inclination judging unit 30 formed of flip-flop (FF)circuits 301 and 302, a ROM 303, and a time adjusting unit (τ) 304, anerror detecting unit 31 formed of the subtracter 311, and a clock phasecalculating unit 32 formed of the EX-OR gate 32.

Numerals 27′ and 28″ represent each integrator and oscillator formingthe clock regenerating circuit 35′ together with the phase componentdetecting unit 26. In this embodiment, the phase component detectingunit 26, the integrator 27′ and the oscillating unit 28′ are used incommon to the A/D converters 23 and 24.

The integrator (loop filter unit) 27′ integrates the output of the phasecomponent detecting unit 26. In this case, like the integrator shown inFIG. 9, the integrator 27′ is formed of a resistor (R) 271 and acapacitor (C) 272. The resistor 271 and the capacitor 272 integrates thephase shift (phase component) of an A/D conversion clock detected by thephase component detecting unit 26.

Furthermore, the oscillating unit (oscillating unit) 28′ generates anA/D conversion clock (signal identification clock) for the A/Dconverters 23 and 24 to the A/D converters 23 and 24 in response to theoutput as a control input from the integrator 27′. Numeral 296represents an amplifier that amplifies information regarding the phaseshift of an A/D conversion clock for the A/D converters 23 and 24 to bedetected by the phase component detecting unit 26 to a predeterminedsignal level.

In the clock regenerating circuit 35′ having the above-mentionedconfiguration, the phase component detecting unit 26 detects the phaseshift of an A/D conversion clock based on the input signal and theoutput signal of the transversal equalizer 25 described in the firstembodiment. Then the integrator 27′ integrates the phase shiftinformation and the amplifier 296 amplifies the result to apredetermined signal level. Then the resultant digital signal is outputto the oscillating unit 28′ without any change.

The oscillating unit 28′ receives the phase shift information as acontrol input and then adjusts automatically the phase shift of an A/Dconversion clock to be sent to the A/D converters 23 and 24, thusproducing an A/D conversion clock to the A/D converters 23 and 24.

As described in the first embodiment, without converting informationregarding the phase shift of an A/D conversion clock detected by thephase component detecting unit 26 from a digital signal form to ananalog signal form and adjusting the phase shift of an A/D conversionclock regenerated based on the signal to be detected by the orthogonaldetecting unit 22 using the analog signal, the clock regeneratingcircuit 35′, as shown in FIG. 29, outputs information regarding thephase shift of an A/D conversion clock as a control input in a digitalsignal form to the oscillating unit 28′, and then adjusts the A/Dconversion clock using the digital signal.

Therefore, although the clock regenerating unit 29 and the phase shifter28 are not arranged like the first embodiment, the very-simplifiedconfiguration can adjust automatically the phase shift of an A/Dconversion clock to be sent to the A/D converters 23 and 24 so that thephase of the A/D conversion clock can be agreed to the optimum phase atwhich the opening of the eye pattern is opened maximumly. Thus theaccuracy of the A/D conversion process by the A/D converters 23 and 24can be improved greatly.

FIG. 30 is a block diagram illustrating the detailed configuration ofthe clock regenerating circuit 35A′ (the phase component detecting unit26, the integrator 27′, the amplifier 296, and the oscillating unit28A′) in the case where the phase component detecting unit 26 shown inFIG. 29 includes the inclination judging unit 30A in the firstembodiment shown in FIG. 14 which samples an Ich signal at intervals ofthe time “T/2” with two-fold high speed clocks and then detects theinclination of the Ich signal. In this case, the inclination judgingunit 30A, as shown in FIG. 15, is formed of the flip-flop (FF) circuits305 and 306 and the COMP (comparing unit) 307.

The A/D converter 23′ is a high speed A/D converter which calculateswith two-fold high speed clocks. The oscillating unit 28A′ is ahigh-speed voltage-controlled oscillating unit (VCO) which calculateswith two-fold high speed clocks (2f).

In the clock regenerating circuit 35A′ with the above-mentionedconfiguration shown in FIG. 30, the inclination judging unit 30A in thephase component detecting unit 26 shown in FIGS. 14 and 15 samples anIch signal at intervals of the time “T/2” to detect the inclination ofthe Ich signal and the error detecting unit (subtracter 311) 31 obtainsa signal error of the Ich signal based on the input signal and theoutput signal of the transversal equalizer 25. Then the clock phasecalculating unit (EX-OR gate 322) 32 subjects the inclination of theresultant Ich signal and the signal error to a calculation (exclusive ORcalculation) to detect the phase shift (phase component) of an A/Dconversion clock.

The phase shift information is integrated by the integrator 271. Thenthe result is amplified to a predetermined signal level by the amplifier296 and then sent to the oscillating unit 28A′ as it is in a digitalsignal form. When receiving the phase shift information as a controlunit, the oscillating unit 28A′ adjusts automatically the phase shift ofan A/D conversion clock for the A/D converters 23 and 24, thusoutputting the A/D conversion clock to the A/D converters 23 and 24.

Therefore, even if the clock regenerating unit 29 and the phase shifter28 described in the first embodiment are not arranged, thevery-simplified configuration can adjust automatically the phase shiftof an A/D conversion clock sent to the A/D converters 23 and 24 andsamples an Ich signal at intervals of the time “T/2” with two-foldhigh-speed clocks, thus detecting the inclination of the Ich signal.Hence the phase shift of an A/D conversion clock can be detected moreaccurately.

FIG. 31 is a block diagram illustrating the detailed configuration ofthe clock regenerating circuit 35B′ in the case where the inclinationjudging unit 30B with no high-speed A/D converter applied as describedwith FIGS. 17 and 18 in the first embodiment, instead of the inclinationjudging unit 30A shown in FIG. 30.

Hence, in this case, the oscillating unit 28B′ which calculates withbasic clocks is used as an oscillating unit.

In the clock regenerating circuit 35B′ with the above-mentionedconfiguration which does not include the clock regenerating unit 29 andthe phase shifter 28 described in the first embodiment, thevery-simplified configuration can adjust automatically the phase shiftof an A/D conversion clock applied to the A/D conversion converters 23and 24.

In this case, even if the A/D converter 23′ operated with high-speedclocks described in FIG. 30 and the delaying circuit such as a flip-flop(FF) circuit are not used, the Ich signal can be sampled at intervals ofthe time “T/2” by supplying clocks from the delaying unit 37 to the A/Dconverters 23A and 23B, the clocks being different in phase by “T/2” (ora different phase shift) from each other, as described with FIGS. 17 and18. Hence the further-simplified configuration can detect accurately theinclination of the Ich signal so that the phase shift of an A/Dconversion clock can be detected more accurately.

Hence the phase shift of an A/ID A/D conversion clock for the A/Dconverters 23A, 23B, and 24 can be adjusted automatically and with highaccuracy to supply to the identifying units (A/D converters) 23A, 23B,and 24.

FIGS. 32 and 33 are block diagrams each illustrating anotherconfiguration of the clock regenerating circuit 35′ shown in FIG. 28. Inthe clock regenerating circuit 35C′ shown in FIGS. 32 and 33, asdescribed with FIGS. 12 and 13, the phase component detecting unit(clock phase detecting unit) 26A and the integrator (loop filter unit)27A′ are arranged to the identifying unit 23 while the phase componentdetecting unit (clock phase detecting unit) 26B and the integrator (loopfilter unit) 27B′ are arranged to the identifying unit 24. Theoscillating unit (oscillating unit) 28B′ is used in common to theidentifying units (A/D converters) 23 and 24. The identifying unit 23(part of the identifying units) is connected to the oscillating unit28B′ via the phase shifter 28A, in the manner similar to that shown inFIGS. 7 and 12. The output of the integrator 27A′ or 27B′ is supplied asa control input to the phase shifter 28A or the oscillating unit 28B′.Numeral 296 represents an amplifier that amplifies information regardingthe phase shift of an A/D conversion clock for the A/D converters 23 and24 detected by the phase component detecting unit 26B to a predeterminedsignal level.

In brief, the clock regenerating circuit 35C′ shown in FIGS. 32 and 33is formed in a digital circuit configuration by using the oscillatingunit 28B′ and the amplifier 296 in the clock regenerating unit 29 of theclock regenerating circuit 35A shown in FIGS. 12 and 13.

In the clock regenerating circuit 35C′, the phase component detectingunit 26A arranged to the A/D converter 23 detects the phase shift of anA/D conversion clock to the A/D converter 23 and then the integrator27A′ integrates the result. The phase component detecting unit 26Barranged to the A/D converter 24 detects the phase shift of an A/Dconversion clock to the A/D converter 24 and then the integrator 27B′integrates the result. The outputs of the integrators 27A′ and 27B′ aresupplied as control inputs to the phase shifter 28A or oscillating unit28B′.

The oscillating unit 28B′ adjusts its oscillation frequency based on theinformation regarding the phase shift of the A/D conversion clock toadjust automatically the phase shift of the A/D conversion clock. Thenthe resultant A/D conversion clock is supplied to the A/D converter 24.The phase shifter 28A adjusts the phase of a piece of the phase shiftinformation supplied to the oscillating unit 28B′ and then supplies theresult to the A/D converter 23.

According to the clock regenerating circuit 35C′, the phase shift of anA/D conversion clock for the A/D converter 23 is detected by the phasecomponent detecting unit 26A corresponding to the A/D converter 23 andthen supplied as a control signal for the oscillating unit 28B′ to theoscillating unit 28B′, whereas the phase shift of an A/D conversionclock for the A/D converter 24 is detected by the phase componentdetecting unit 26B corresponding to the A/D converter 24 and thensupplied as a control signal for the oscillating unit 28B′ to theoscillating unit 28B′. Hence, the process accuracy of each of theidentifying units 23 and 24 can be more improved, compared with theclock regenerating circuit 35 described with FIGS. 28 and 29.

FIG. 34 is a block diagram illustrating another configuration of theclock regenerating circuit 35′ shown in FIG. 28. FIG. 35 is a blockdiagram illustrating another configuration of the clock regeneratingcircuit 35′ shown in FIG. 29. The clock regenerating circuit 35D′, shownin FIGS. 34 and 35, includes a composing unit 51 formed of a multiplier511, in addition to the orthogonal detecting unit 22, the identifyingunits (A/ID converters) 23 and 24, the equalizer (transversal equalizer)25, phase component detecting units (clock phase detecting units) 26Aand 26B, the integrator (loop filter unit) 27′, and the oscillating unit28′ shown in FIGS. 28 and 29.

In this case, the phase component detecting unit 26A is arrangedcorresponding to the A/D converter 23 while the phase componentdetecting unit 26B is arranged corresponding to the A/D converter 24.The oscillating unit 28′ and the integrator 27′ are used in common tothe identifying units 23 and 24. The composing unit 51 is arranged tocompose the output of the phase component detecting unit 26A with theoutput of the phase component detecting unit 26B. The output of thecomposing unit 51 is input to the integrator 27′.

In the clock regenerating circuit 35D′, the phase component detectingunit 26A corresponding to the A/D converter 23 detects the phase shiftof an A/D conversion clock (signal identification clock) for the A/Dconverter 23 while the phase component detecting unit 26B correspondingto the A/D converter 24 detects the phase shift of an A/D conversionclock (signal identification clock) for the A/D converter 24. Themultiplier 511 in the composing unit 51 multiplies the output of thephase component detecting unit 26A by the output of the phase componentdetecting unit 26B to supply as an input to the integrator 27′ and theoscillating unit 28′ which are arranged in common to the A/D converters23 and 24.

Hence the phase shift of the A/D conversion clock supplied from theoscillating unit 28′ to the A/D converters 23 and 24 can be adjustedautomatically and with high accuracy so that the phase of the A/Dconversion clock can be agreed more accurately to the phase in which theopening portion of the eye pattern of a signal is opened to its maximumat the optimum A/D conversion timing. The composing unit 51 may beformed in an analog circuit configuration including resistors 512 and513 as shown in FIG. 36.

FIG. 37 is a block diagram illustrating another configuration of theclock regenerating circuit 35′ shown in FIG. 28. FIG. 38 is a blockdiagram illustrating another configuration of the clock regeneratingcircuit 35′ shown in FIG. 29. In FIGS. 37 and 38, like numeralsrepresent like elements shown in FIGS. 28 and 29.

The clock regenerating circuit 38E′ shown in FIGS. 37 and 38 includesanother phase component detecting unit 52 and a composing unit 51′ inaddition to the phase component detecting unit 26 shown in FIGS. 28 and29.

Another phase component detecting unit (second clock phase detectingunit) 52 detects the phase shift (phase component) of an A/D conversionclock to the identifying units (A/D converters) 23 and 24 in a methoddifferent from the phase component detecting unit 26. In this case, asshown in FIG. 38, the phase component detecting unit 52 includes anEX-OR gate 521 that subjects both an error signal of an Ich signal whichhas been equalized by the transversal equalizer 25 and the inclinationof an Ich signal obtained by the inclination judging unit 30 to anexclusive OR operation. Numeral 522 represents a time adjusting unit (τ)that matches the input timing of two kinds of signals to be calculatedby the EX-OR gate 521.

The composing unit 51′ composes the output of the phase componentdetecting unit 26 with the output of another phase component detectingunit 52 and then outputs the result to the integrator 27′ as an input.In this case, as shown in FIG. 38, the composing unit 51′ is formed ofthe multiplier 511. As shown in FIGS. 37 and 38, the integrator 27′ andthe oscillating unit 28′ are used in common to the A/D converters 23 and24.

In the clock regenerating circuit 35E′, another phase componentdetecting unit 52 detects the phase shift of an A/D conversion clock tothe A/D converters 23 and 24 in a method different from the phasecomponent detecting unit 26. Then the multiplier 511 in the composingunit 51′ multiplies (composes) information regarding the phase shift ofan A/D conversion clock by information regarding the phase shift of anA/D conversion clock detected by the phase component detecting unit 26as described in the first embodiment and then supplies as an input theresult of the integrator 27′.

In such a manner, the phase shift information (phase componentinformation) of an A/D conversion clock can be output with higheraccuracy to the oscillating unit 28′ supplying A/D conversion clocks tothe A/D converters 23 and 24 via the integrator 27′. Hence the phaseshift of an A/D conversion clock can be adjusted automatically andaccurately so that the A/D converters 23 and 24 can greatly improve theaccuracy of the A/D conversion process.

FIG. 39 is a block diagram illustrating another configuration of theclock regenerating circuit 35′ shown in FIG. 28. FIG. 40 is a blockdiagram illustrating another configuration of the clock regeneratingcircuit 35′ shown in FIG. 29. In FIGS. 39 and 40, like numeralsrepresent like elements shown in FIGS. 28 and 29.

The clock regenerating circuit 35F′ shown in FIGS. 39 and 40 includesanother phase component detecting unit 52, a selecting unit 53, and asignal quality judging unit 54, in addition to the orthogonal detectingunit 22, the identifying units (A/D converters) 23 and 24, the equalizer(transversal equalizer) 25, the phase component detecting unit 26, theintegrator 27′ and the oscillating unit 28′, previously described withFIGS. 28 and 29.

Another phase component detecting unit (second clock phase detectingunit) 52 corresponding to that shown in FIGS. 37 and 38 detects thephase shift of an A/D conversion clock in a method different from thephase component detecting unit 26. The phase component detecting unit52, as shown in FIG. 40, includes an EX-OR gate 521 that subjects theerror signal of an Ich signal equalized by the transversal equalizer 25and the inclination of an Ich signal obtained by the inclination judgingunit 30 to an exclusive OR operation.

The selecting unit 53 outputs selectively as an input the output fromthe phase component detecting unit 26 and the output from another phasecomponent detecting unit 52 to the integrator 27′, according to thecontrol signal from the signal quality judging unit 54 (to be describedlater). In this case, the selecting unit 53 is formed as a selector(SEL) as shown in FIG. 40.

The signal quality judging unit 54 supplies a signal which controlsselectively the output signal of the selecting unit 53. In this case,the signal quality judging unit 54, as shown in FIG. 40, is formed as aframe synchronizing circuit that judges a signal quality through anerror correction to output a frame synchronization signal as a controlsignal.

In the clock regenerating circuit 3SF′, another phase componentdetecting unit 52 detects the phase shift of an A/D conversion clock tothe A/D converters 23 and 24 in a method different from the phasecomponent detecting unit 26. The SEL 53 supplies selectively, as aninput, information regarding the phase shift of an A/D conversion clockobtained by another phase component detecting unit 52 and informationregarding the phase shift of an A/D conversion clock detected by thephase component detecting unit 26 described in the first embodiment tothe integrator 27′ according to the control signal from the framesynchronizing circuit 54.

In this case, information regarding the phase shift of an A/D conversionclock (phase component information) is output with higher accuracy tothe oscillating unit 28′ supplying A/D conversion clocks to the A/Dconverters 23 and 24 via the integrator 27′. Thus the phase shift of anA/D conversion clock is adjusted automatically and accurately so thatthe A/D converters 23 and 24 can greatly improve the accuracy in the A/Dconversion process.

FIG. 41 is a block diagram illustrating another configuration of theclock regenerating circuit 35G′ shown in FIG. 28. FIG. 42 is a blockdiagram illustrating another configuration of the clock regeneratingcircuit 35G′ shown in FIG. 29. The clock regenerating circuit 35G′ shownin FIGS. 41 and 42 includes a selecting unit 46 and a random pulsegenerating unit 47, in addition to the phase component detecting unit26, the oscillating unit 28′ and the amplifier 296, and the integrator27′ shown in FIGS. 28 and 29.

The selecting unit 46 corresponds to that in the first embodiment shownin FIGS. 26 and 27. The random pulse generating unit (test signalgenerating unit) 47 corresponds to that in the first embodiment shown inFIGS. 26 and 27. In this case, the selecting unit 46 formed as aselector (SEL) outputs selectively the output of the phase componentdetecting unit 26 and the output of the random pulse generating unit 47in response to the test (adjustment) / normal switching signal to theintegrator 27′. The random pulse generating unit 47 is formed of fourflip-flop (FF) circuits 471 to 474 and an EX-OR gate 475. The randompulse generating unit 47 creates a chain of pulses at the middle valueof the phase shift of an A/D conversion clock detected by the phasecomponent detecting unit 26.

In brief, the clock regenerating circuit 35G′ is formed as a digitalcircuit form, instead of the analog clock regenerating circuit shown inFIGS. 26 and 27.

The clock regenerating circuit 35G′ can supply selectively as an inputthe test signal of the random pulse generating unit 47 and the output ofthe phase component detecting unit 26 to the integrator (loop filterunit) 27′, according to a test (adjustment) / normal switching signal.

Hence, the phase shift of an A/D conversion clock to the A/D converters23 and 24 can be tested and adjusted very easily.

(d) Third Embodiment of the Present Invention:

FIG. 43 is a block diagram illustrating the configuration of each of theclock phase detecting circuit and the clock regenerating circuitarranged in multiplex radio equipment shown in the third embodimentaccording to the present invention. Referring to FIG. 43, numeral 22represents an orthogonal detecting unit; 23 and 24 represent identifyingunits; 27 represents an integrator; 28 represents a phase shifter; 29represents a clock regenerating unit; and 61 represents a phasecomponent detecting unit. In this embodiment, the clock regeneratingcircuit 68 is basically formed of the phase component detecting unit 61,the integrator 27, the phase shifter 28, and the clock regenerating unit29.

The orthogonal detecting unit 22, the identifying units 23 and 24, theintegrator 27, the phase shifter 28, and the clock regenerating unit 29correspond respectively to those with the same numerals shown in thefirst embodiment. The orthogonal detecting unit 22 detects an IF bandsignal and outputs two kinds of signals including an Ich signal and aQch signal different in phase by 90° (perpendicular to) from each other.In this embodiment, each of the identifying units 23 and 24 formed as anA/D converter (to be described later) A/D-converts (identifies) theoutput of the orthogonal detecting unit 22 (or a signal obtained bydemodulating a multilevel orthogonal modulation signal) at apredetermined level.

In this embodiment, as shown in FIG. 44, the orthogonal detecting unit22 includes hybrid circuits (H) 221 and 222, phase detectors 223 and224, roll-off filters 225 and 226, and a local oscillating unit 227. Theidentifying units 23 and 24 are respectively arranged as two A/Dconverters corresponding to two kinds of (plural) signals (an Ich signaland a Qch signal) obtained by demodulating a multilevel orthogonalmodulation signal.

The integrator (averaging unit) 27 which is arranged between the phasecomponent detecting unit 61 and the phase shifter 28 (to be describedlater) averages the output of the phase component detecting unit 61. Inthis case, as shown in FIG. 44, the integrator 27 is formed of aresistor (R) 271 and a capacitor (C) 272.

The phase shifter (phase adjusting unit) 28 adjusts the phase of the A/Dconversion clock (signal identification clock) to the identifying units(A/D converters) 23 and 24 regenerated by the clock regenerating unit 29to supply to the identifying units 23 and 24. The clock regeneratingunit 29 regenerates an A/D conversion clock for the identifying units 23and 24 from an IF signal (multilevel orthogonal modulated signal) to bedetected by the orthogonal detecting unit 22 and then supplies it to theidentifying units 23 and 24. In this case, as shown in the firstembodiment, the clock regenerating unit 29 is formed of a PLL circuit293 including a square detecting unit 291, a filter 292, a phasedetector (PD) 294, a loop filter 295, an amplifier 296, and anoscillating unit 297.

The phase component detecting unit (clock pulse detecting circuit(unit)) 61 detects the phase shift (phase component) of an A/Dconversion clock based on information regarding the phase difference ofan A/D conversion clock supplied to the identifying units 23 and 24 andinformation regarding the signal error differential obtained by theidentifying unit 23 and then supplies the result to the integrator 27being a constituent element of the clock regenerating circuit 68. Thephase component detecting unit 61 is formed of a phase differentialdetecting unit 62, an error differential detecting unit 63, a clockphase calculating unit 64, and flip-flop (FF) circuits 65 and 66.

The phase differential detecting unit 62 detects information regardingthe phase difference of an A/D conversion clock supplied to theidentifying units 23 and 24. The error differential detecting unit 63detects information regarding the signal error differential of an Ichsignal obtained by the identifying unit 23. In this embodiment, as shownin FIG. 44, each of the phase differential detecting unit 62 and theerror differential detecting unit 63 is formed as a subtracter. The FFcircuits 65, 65′, and 66, 66′ are used to delay input signals by apredetermined delay amount.

The clock phase calculating unit 64 calculates the output of the phasedifferential detecting unit 62 and the output of the error differentialdetecting unit 63 to detect the phase shift of an A/D conversion clock.In concrete, the clock phase calculating unit 64 is formed as a divider(dividing unit) 641 that subjects the output of the phase differentialdetecting unit 62 and the output of the error differential detectingunit 63 to a dividing process.

The D/A converter 33 converts information regarding the phase shift ofan A/D conversion clock detected by the phase component detecting unit61 from a digital signal to an analog signal. The converting circuit 67converts the phase difference information of an A/D conversion clocksupplied to the identifying units 23 and 24 into a predetermined signal.In this case, the converting circuit 67, as shown in FIG. 44, is formedof a counter 671 operating with high speed clocks (CLK). In thisembodiment, the phase component detecting unit 61, the integrator 27,the phase shifter 28, and the clock regenerating unit 29 are used incommon to the identifying units 23 and 24.

Next, the operation of the above-mentioned clock regenerating circuit 68being the main portion of the present invention will be explained belowin detail with reference to FIG. 44.

In the phase component detecting unit 61, the FF circuit 65′ receives apredetermined signal obtained by converting the phase error of an A/Dconversion clock to be supplied to the A/D converters 23 and 24 by theconverting circuit 67. The FF circuit 66′ receives the signal error(signal error information) of an Ich signal A/D-converted by A/Dconverter 23.

The FF circuits 65, 65′ and 66, 66′ delay the above signals by apredetermined amount and then input the results to the subtracters 62and 63. At this time, the subtracter 62 receives the current phaseinformation φ(t2) (e.g. at the time t2) and the past phase informationφ(t1) (e.g. at the time t1) delayed by the FF circuit 65. The subtracter63 receives the error signal e(t2) of a current Ich signal (e.g. at thetime t2) and the error signal e(t1) of a past Ich signal (e.g. that thetime t1) delayed by the FF circuit 66.

Each of the subtracters 62 and 63 performs a subtracting process of aninput signal. The subtracter 62 produces the phase differenceinformation [φ(t2)−φ(t1)] of an A/D conversion clock and the subtracter63 produces the signal error differential information [(e(t2)−e(t1)] ofthe Ich signal. The divider (clock phase calculating unit 64) 641subjects the phase difference information [φ(t2)−φ(t1)] and the signalerror differential information [(e(t2)−e(t1)] to a division process.

As a result, the phase component detecting unit 61 produces informationAt regarding the phase shift of an A/D conversion clock expressed by thefollowing formula:Δt=[e(t2)−e(t1)]/[(φt2)−(φt1)]

In other words, where the phase of an A/D conversion clock shifts fromthe position of a signal point on the eye pattern in the above-mentionedprocess, bits lower than the signal bit (D1, D2) of a base band signalwhich is obtained by demodulating a multilevel orthogonal modulatedsignal called 16 QAM error bits (D3, D4, . . . ) shown in FIG. 45increase as shown in FIG. 46. Hence the direction (phase shift Δt) inwhich the phase of an A/D conversion clock is adjusted is obtained bydifferentiating the curve between [phase error φ(t1), signal errore(t1)] at the time t1 and [phase error φ(t2), signal error e(t2)] at thetime t2 on the clock phase to signal error curve shown in FIG. 46.

Thereafter the information (Δt) regarding the phase shift of an A/Dconversion clock detected above is averaged by the integrator 27. Thenthe averaged information is supplied as a phase adjustment and controlsignal to the phase shifter 28 to adjust the phase shift of an A/Dconversion clock regenerated by the clock regenerating unit 29.

Hence since the phase shifter 28 can adjust automatically and withhigher accuracy the phase shift of an A/D conversion clock to the A/Dconverters 23 and 24, the accuracy of an A/D conversion process by theA/D converters 23 and 24 can be greatly improved.

The equalizer (transversal equalizer) 25 described in the first andsecond embodiments is arranged on the rear stage of each of the A/Dconverters 23 and 24, as shown in FIG. 44.

In the clock regenerating circuit 68 in this embodiment, if the phasedifferential information of the phase differential detecting unit 62 andthe signal error information of the error differential detecting unit 63are expressed only by polarities as described in the first embodiment,the clock phase calculating unit 64, as shown in FIGS. 47 and 48, can beformed as the EX-OR gate (exclusive OR element) 642 instead of thedivider 641. Hence the phase shift (phase component) of an A/Dconversion clock can be detected by a more-simplified configuration. InFIGS. 47 and 48, the same numerals as those in FIGS. 43 and 44 representthe same elements.

FIG. 49 is a block diagram illustrating another configuration of theclock regenerating circuit 68 shown in FIGS. 43 and 44. In the clockregenerating circuit 68A shown in FIG. 49, the clock regenerating unit29 is arranged in common to the identifying units 23 and 24. Like thephase shifter 28, the integrator 27, and the phase component detectingunit 61 shown in FIGS. 43 and 44, the phase shifter 28A, the integrator27A, and the phase component detecting unit 61A are arranged to the A/Dconverter 23 while the phase shifter 28B, the integrator 27B, and thephase component detecting unit 61B are arranged to the A/D converter 24.

In the clock regenerating circuit 68A shown in FIG. 49, as describedwith FIGS. 43 and 44, the phase component detecting unit 61A arranged tothe identifying unit 23 detects the phase shift (phase component) of asignal identification clock (A/D conversion clock) to the identifyingunit 23 based on phase difference information of a signal identificationclock (A/D conversion clock) supplied to the identifying unit 23 andsignal error differential information output from the identifying unit23. The phase component detecting unit 61B arranged to the identifyingunit 24 detects the phase shift (phase component) of a signalidentification clock (A/D conversion clock) to the identifying unit 24based on phase difference information of a signal identification clock(A/D conversion clock) supplied to the identifying unit 24 and signalerror differential information output from the identifying unit 24.

The integrator 27A receives and averages information regarding the clockphase shift detected by the phase component detecting unit 61A. Theintegrator 27B receives and averages information regarding the clockphase shift detected by the phase component detecting unit 61B. Theneach of the phase shifters 28A and 28B receives the averaged result as aphase adjustment and control signal to adjust the phase shift of asignal identification clock which is regenerated from the IF signal tobe detected by the orthogonal detecting unit 22 by the clockregenerating unit 29 used in common to the identifying units 23 and 24.

Thus, the phase shifter 28A can adjust the clock phase shift to theidentifying unit 23 and the phase shifter 28B can adjust the clock phaseshift to the identifying unit 24. Hence the accuracy of the signalidentifying process in the identifying units 23 and 24 can be greatlyimproved.

Like the first embodiment described with FIGS. 26 and 27, the clockregenerating circuit 68 (or 68A), as shown in FIG. 50, can include a PNpattern generating circuit (random pulse generating unit: a test signalgenerating unit) 47 and a selector (SEL: selecting unit) 46 to input theoutput of the SEL 46 to the phase shifter 28 via the integrator 27.

In this case, the PN pattern generating circuit 47 is formed of fourflip-flop (FF) circuits 471 to 474 and an EX-OR gate 475. The PN patterngenerating circuit 47 generates a test random pulse to set the phaseshift of an A/D conversion clock by the phase component detecting unit61 (or 61A, 61B) to the center value of a detection result. The SEL 46outputs selectively the output of the phase component detecting unit 61(or 61A, 61B) and the output of the PN pattern generating circuit 47 inresponse to a test/normal switching signal. In FIG. 49, the samenumerals as those shown in FIG. 44 represent the same elements.

When the clock regenerating circuit 68 with the above-mentionedstructure as shown in FIG. 50 is adjusted and tested, the adjustmentsignal is input to the SEL 46. Instead of the phase shift (phasecomponent) of an A/D conversion clock to the A/D converters 23 and 24 tobe detected by the phase component detecting unit 61 as described withFIGS. 43 to 46, the SEL 46 outputs selectively the random pulse (testsignal) generated from the PN pattern generating circuit 47. Then theintegrator 27 averages the selected output to supply the result as aphase adjustment and control signal for the phase shifter 28 to thephase shifter 28.

Hence the phase shifter 28 can adjust and test very easily the phaseshift of an A/D conversion clock sent to the A/D converters 23 and 24.

(e) Fourth Embodiment of the Present Invention:

FIG. 51 is a block diagram illustrating the configuration of each of theclock phase detecting unit and the clock regenerating circuit arrangedin multiplex radio equipment according to the fourth embodiment of thepresent invention. Referring to FIG. 51, numeral 22 represents anorthogonal detecting unit; 23 and 24 represent identifying units; and 61represents a phase component detecting unit. These elements correspondto those shown in the third embodiment. Numeral 27′ represents anintegrator and 28′ represents an oscillating unit. In this embodiment,the phase component detecting unit 61, the integrator 27′ and theoscillating unit 28′ provide the clock regenerating circuit 68′.

The orthogonal detecting unit 22, the identifying units 23 and 24, theintegrator 27′ and the oscillating unit 28′ correspond to elements withthe same numerals described in the second embodiment, respectively. Theorthogonal detecting unit 22 outputs two kinds of signals including anIch signal and a Qch signal which are different in phase (perpendicularto each other) by 90° from each other by detecting an IF band signal. Asshown in FIG. 52, the orthogonal detecting unit 22 is formed of hybridcircuits (H) 221 and 222, phase detectors 223 and 224, roll-off filters225 and 226, and a local oscillating unit 227. Each of the identifyingunits 23 and 24 is formed as an A/D converter that A/D-converts(identifies) the output of the orthogonal detecting unit 22 (a signaldemodulated by the multilevel orthogonal modulation signal) at apredetermined level.

The integrator (loop filter unit) 27′ which integrates the output of thephase component detecting unit 61 (to be described later) is formed of aresistor (R) 271 and a capacitor (C) 272, as shown in FIG. 52. Theresistor 271 and the capacitor 272 integrate the phase shift (phasecomponent) information of an A/D conversion clock detected by the phasecomponent detecting unit 61.

The oscillating unit (oscillating unit) 28′ receives the output of theintegrator 27′ as a control input which adjusts the phase shift of anA/D conversion clock and then outputs a signal identification clock (A/Dconversion clock) to the identifying units (A/D converters) 23 and 24.

The phase component detecting unit (clock phase detecting circuit(unit)) 61 detects the phase shift (phase component) of an A/Dconversion clock in response to the phase difference information of anA/D conversion clock supplied to the A/D converters 23 and 24 and signalerror differential information obtained by the A/D converter 23 and thensupplies it to the integrator 27′ being a constituent element of theclock regenerating circuit 68′. The phase component detecting unit 61 isformed of a phase differential detecting unit 62, an error differentialdetecting unit 63, a clock phase calculating unit 64, flip-flop (FF)circuits 65 and 66.

The phase differential detecting unit 62 detects the phase differenceinformation of an A/D conversion clock supplied to the A/D converters 23and 24. The error differential detecting unit 63 detects the signalerror differential information of an Ich signal obtained by theidentifying unit 23. Each of the phase differential detecting unit 62and the error differential detecting unit 63 is formed as a subtracterin this embodiment, as shown in FIG. 52. Each of the FF circuits 65 and65′ delay its input signal by a predetermined amount and each of the FFcircuits 66 and 66′ delay its input signal by a predetermined shift.

The clock phase calculating unit 64 calculates the output of the phasedifferential detecting unit 62 and the output of the error differentialdetecting unit 63 to detect the phase shift of an A/D conversion clock.In concrete, the clock phase calculating unit 64, which is formed of adivider (dividing unit) 641, subjects the output of the phasedifferential detecting unit 62 and the output of the error differentialdetecting unit 63 to a division process.

Referring to FIG. 52, numeral 67 represents a converting circuit thatconverts phase difference information of an A/D conversion clocksupplied to the A/D converters 23 and 24 into a predetermined signal.The converting circuit 67 includes a counter 671 operating with highspeed clocks (CLK). The amplifier 296 amplifies information regardingthe phase shift of an A/D conversion clock detected by the phasecomponent detecting unit 61 to a predetermined signal level. In thisembodiment, the phase component detecting unit 61, the integrator 27,the phase shifter 28, and the clock regenerating unit 29 are used incommon to the identifying units (A/D converters) 23 and 24.

In the clock regenerating circuit 68′ with the above-mentionedconfiguration, the converting circuit 67 converts the phase error of anA/D conversion clock to be supplied to the A/D converters 23 and 24 intoa predetermined signal and then inputs the converted signal to the FFcircuit 65′ in the phase component detecting unit 61. At the same time,the FF circuit 66′ receives the signal error (signal error information)of an Ich signal A/D converted by the A/D converter 23.

The FF circuits 65 and 65′ delays the converted signal by apredetermined shift to input to the subtracter 62. The FF circuits 66and 66′ delays the signal error by a predetermined amount to input tothe subtracter 63. Each of the subtracters 62 and 63 subjects its inputto a subtraction process. The subtracter 62 obtains the phase differenceinformation of an A/D conversion clock while the subtracter 63 obtainsthe signal error differential information of an Ich signal.

The divider 641 (clock phase calculating unit 64) 641 subjects the phasedifference information and signal error differential information to andivision process. As a result, the phase shift information of an A/Dconversion clock can be obtained.

Thereafter, the phase shift information of the above-detected A/Dconversion clock is not converted from the digital signal form to ananalog signal form as described in the third embodiment, but integratedby the integrator 27′ as it is in a digital signal form. The result isamplified by the amplifier 296 to a predetermined signal level. Then theoscillating unit 28′ receives the amplified signal as a control signalto adjust the phase shift on an A/D conversion clock.

In other words, like the third embodiment, the clock regeneratingcircuit 68′ does not convert the phase shift information of an A/Dconversion clock to the A/D converters 23 and 24 to be detected by thephase component detecting unit 61 from a digital signal to an analogsignal to adjust the phase shift of an A/D conversion clock using theanalog signal. Instead, the clock regenerating circuit 68′ outputs thephase shift information of an A/D conversion clock in a digital signalform as a control input to the oscillating unit 28′ and then adjusts thea/D conversion clock using the digital signal.

Consequently, even if the clock regenerating unit 29 and the phaseshifter 28 are not arranged like the third embodiment, thevery-simplified configuration can adjust automatically the phase shiftof an A/D conversion clock to the A/D converters 23 and 24. Thus the A/Dconverters 23 and 24 can greatly improve the accuracy of an A/Dconversion process.

In the clock phase calculating unit 64 in the phase component detectingunit 61 in this embodiment, if the phase differential information fromthe phase differential detecting unit 62 and the signal errorinformation from the error differential detecting unit 63 are simplyexpressed with polarities, an EX-OR gate (exclusive OR element) 642, asshown in FIG. 53, can be arranged instead of the divider 641. Themore-simplified configuration can detect the phase shift (phasecomponent) of an A/D conversion clock. Other constituent elementscorrespond to those described with FIG. 52.

The clock regenerating circuit 68′, shown in FIGS. 52 and 53, can beconstituted more simply by using the converting circuit 67′ formed asthe A/D converter 672 as shown in FIG. 54, instead of the convertingcircuit 67.

Next, FIG. 55 is a block diagram showing another configuration of theclock regenerating circuit 68′ shown in FIGS. 51 to 54. The clockregenerating circuit 68A′ shown in FIG. 55 includes a composing unit 51Aformed of a multiplier 511, in addition to the orthogonal detecting unit22, the identifying units 23 and 24, the phase component detecting units(clock phase detecting units) 61A and 61B, the integrator (loop filterunit) 27′, and the oscillating unit 28′ corresponding to those shown inFIGS. 51 to 54.

In this case, the phase component detecting unit 61A is arrangedcorresponding to the A/D converter 23 and the phase component detectingunit 61B is arranged corresponding to the A/D converter 24. Theoscillating unit 28′ and the integrator 27′ are used in common to theidentifying units 23 and 24. The composing unit 51A is arranged tocompose the output of the phase component detecting unit 61A with theoutput of the phase component detecting unit 61B. The output of thecomposing unit 51A is input to the integrator 27′.

In the clock regenerating circuits 68A′, the phase component detectingunit 61 corresponding to the A/D converter 23 detects the phase shiftinformation of a signal identification clock for the A/D converter 23and the phase component detecting unit 61 corresponding to the A/Dconverter 24 detects the phase shift information of a signalidentification clock for the A/D converter 24. The multiplier 511 in thecomposing unit 51A multiplies the output from the phase componentdetecting unit 61A by the output of the phase component detecting unit61B and then supplies the result as an input to the integrator 27′ andthe oscillating unit 28′ used in common to the identifying units 61A and61B.

Hence the phase shift of a signal identification clock supplied from theoscillating unit 28′ to the identifying units 23 and 24 can be adjustedindependently and with higher accuracy to the identifying units 23 and24. The composing unit 51A can be constituted in an analog circuit formor a digital circuit form. The detail configuration of each element issimilar to that described with FIGS. 52 to 54. Hence the duplicateexplanation will be omitted here.

FIG. 56 is a block diagram illustrating another configuration of theclock regenerating circuit 68′ shown in FIGS. 51 to 54. In the clockregenerating circuits 68′B shown in FIG. 56, the phase componentdetecting unit (clock phase detecting unit) 61A and the integrator (loopfilter unit) 27A′ are arranged to the identifying unit 23, whereas thephase component detecting unit, the clock phase detecting unit 61B andthe integrator (loop filter unit) 27B′ are arranged to the identifyingunit 24. The oscillating unit (oscillating unit) 28B′ is used in commonto the identifying units (A/D converters) 23 and 24. The identifyingunit 23 is connected to the oscillating unit 28B′ via the phase shifter28 similar to that described in the third embodiment. The output of theintegrator 27A′ is supplied as a control input to the phase shifter 28or the oscillating unit 28B′, whereas the output of the integrator 27B′is supplied as a control input to the phase shifter 28 or theoscillating unit 28B′. Numeral 296 represents an amplifier whichamplifies the phase shift information of a signal identification clockfor the identifying units 23 and 24 detected by the phase componentdetecting unit 61B to a predetermined signal level.

In the clock regenerating circuit 68B′, like the third embodiment, thephase component detecting unit 61A detects information regarding thephase shift of a signal identification clock to the identifying unit 23and the integrator 27A′ integrates the detected information. On theother hand, the phase component detecting unit 61B detects informationregarding the phase shift of a signal identification clock to theidentifying unit 24 and the integrator 27B′ integrates the detectedinformation. Then the result is supplied as a control input to the phaseshifter 28 or the oscillating unit 28B′.

The oscillating unit 28B′ adjusts automatically its oscillationfrequency and the clock phase shift, based on information regarding thephase shift of a signal identification clock and supplies the result tothe identifying unit 24. The phase shifter 28 adjusts the phase of apiece of the phase shift information supplied to the oscillating unit28B′ and then supplies the result to the identifying unit 23.

As described above, according to the clock regenerating circuit 68A′,the phase component detecting unit 61A arranged corresponding to theidentifying unit 23 detects the phase shift of a signal identificationclock to the identifying unit 23 to supply the result as a controlsignal for the oscillator 28B′ or the phase shifter 28 to theoscillating unit 28B′ via the integrator 27A′ while the phase componentdetecting unit 61B arranged corresponding to the identifying unit 24detects the phase shift of a signal identification clock to theidentifying unit 24 to supply the result as a control signal foroscillator 28B′ or the phase shifter 28 to the oscillating unit 28B′ viathe integrator 27B′. Hence the accuracy of the signal identifyingprocess in the identifying units 23 and 24 can be further improved.

FIG. 57 is a block diagram illustrating another configuration of theclock regenerating circuit 68′ shown in FIGS. 51 to 54. The clockregenerating circuit 68C′ shown in FIG. 57 additionally includes anotherphase component detecting unit 52′. The integrator (loop filter unit)27′ and the oscillating unit (oscillating unit) 28′, similar to thoseshown in FIGS. 51 to 54, are used in common to the identifying units 23and 24. A composing unit 51B is arranged in the clock regeneratingcircuit 68° C.

Another phase component detecting unit (second clock phase detectingunit) 52′ is identical to another phase component detecting unit 52shown in FIGS. 37 and 38 in the second embodiment. In this embodiment,information regarding the phase shift of a signal identification clockcan be detected in a method different from that by the phase componentdetecting unit 61. The composing unit 51B composes the output of anotherphase component detecting unit 52′ with the output of the phasecomponent detecting unit 52.

In such a manner, in the clock regenerating circuit 68C′, another phasecomponent detecting unit 52 detects information regarding the phaseshift of a signal information clock to the identifying units 23 and 24in a method different from the phase component detecting unit 61. Thenthe multiplier 511 in the composing unit 51B multiplies (composes) theinformation regarding the signal identification clock by the informationregarding the phase shift of a signal identification clock, based on thephase difference information and the signal error differentialinformation detected by the phase component detecting unit 26 describedin the third embodiment, and then supply the result to the integrator27′.

The information regarding the phase shift of an A/D conversion clock(phase component information) can be output with higher accuracy to theoscillating unit 28′ which supplies signal identification clocks to theidentifying units 23 and 24 via the integrator 27′. Hence the phaseshift of a signal identification clock sent to the identifying units 23and 24 can be adjusted automatically and with high accuracy so that theidentifying units 23 and 24 can greatly improve the accuracy in thesignal identifying (A/D conversion) process.

FIG. 58 is a block diagram illustrating another configuration of theclock regenerating circuit 68′ described with FIGS. 51 to 54. The clockregenerating circuit 68D′ shown in FIG. 58 includes another phasecomponent detecting unit (second clock phase detecting unit) 52′described with FIG. 57. The integrator (loop filter unit) 27′ and theoscillating unit (oscillating unit) 28′ similar to those shown in FIGS.51 to 54 are used in common to the identifying units 23 and 24. Theclock regenerating circuit 68D′ also includes a selecting unit 53′. Thesignal quality judging unit 54′ supplies a control signal to select theoutput from the selecting unit 53′. In concrete, the signal qualityjudging unit 54′ is formed as a frame synchronizing circuit that judgesthe signal quality through an error correction process as described withFIG. 40 and then outputs the frame synchronization signal as a controlsignal.

The selecting unit 53′ selectively outputs the output of the phasecomponent detecting unit 61 and the output of another phase componentdetecting unit 52′ to the integrator 27′ according to the control signal(e.g. a frame synchronization signal) from the signal quality judgingunit 54′.

In the clock regenerating circuit 68D′ with the above-mentionedconfiguration, another phase component detecting unit 52′ detects thephase shift of an A/D conversion clock to the A/D converters 23 and 24in a method different from that of the phase component detecting unit61. The selecting unit 53′ selectively inputs the information regardingthe phase shift of an A/D conversion clock detected by another phasecomponent detecting unit 52′ and the information regarding the phaseshift of an A/D conversion clock detected by the phase componentdetecting unit 61 described in the first embodiment to the integrator27′ according to the control signal from the signal quality judging unit54′.

In this case, the information regarding the phase shift of an A/Dconversion clock (phase component information) can be supplied withhigher accuracy to the oscillating unit 28′ which supplies signalidentification clocks to the identifying units 23 and 24 via theintegrator 27′, the accuracy of the signal identification process in theidentifying units 23 and 24 can be greatly improved by adjustingautomatically and accurately the phase shift of a signal identificationclock.

FIG. 59 is a block diagram illustrating another configuration of theclock regenerating circuit 68′ shown in FIGS. 51 to 54. The clockregenerating circuit 68E′ shown in FIG. 59 includes the selector (SEL:selecting unit) 46′ and the PN pattern generating circuit 47′, inaddition to the phase component detecting unit 61, the oscillating unit28′, the amplifier 296, and the integrator 27′ similar to those shown inFIG. 53. The selector 46′ corresponds to the selector (SEL) 46 shown inFIG. 49 in the third embodiment and the PN pattern generating circuit47′ corresponds to the PN pattern generating circuit 47 shown in FIG. 49in the third embodiment.

In brief, the clock regenerating circuit 68E′ is obtained by convertingthe clock regenerating circuit 68 in an analog circuit form describedwith FIG. 53 into a digital circuit form. In FIG. 59, the numerals asthose shown in FIG. 50 represent like elements.

Thus the clock regenerating circuit 68E′ supplies selectively the testsignal from the PN pattern generating circuit 47′ and the output fromthe phase component detecting unit 61 to the integrator (loop filterunit) 27′, according to a test (adjustment) / normal switching signal.

Therefore, the phase shift of an A/D conversion clock (signalidentification clock) to the A/D converters (identifying units) 23 and24 can be tested and adjusted very easily.

1. A clock phase detecting circuit arranged in a receiving unit ofmultiplex radio equipment, comprising: an identifying circuit foridentifying a signal at a predetermined identification level, saidsignal being obtained by demodulating a multilevel orthogonal modulatedsignal; a clock regenerating circuit for regenerating a signalidentification clock for said identifying circuit to supply said clockto said identifying circuit; an equalizing circuit for subjecting saidsignal obtained by demodulating the multilevel orthogonal modulatedsignal to an equalizing process; and a clock phase detecting unit fordetecting a phase component of said signal identification clock based onerrors between input and output signals of said equalizing circuit andthen for supplying said phase component to said clock regeneratingcircuit; wherein said clock phase detecting unit includes: an errordetecting unit for detecting a signal error between said input andoutput signals of said equalizing circuit: and a clock phase calculatingunit for detecting the phase component of said signal identificationclock by calculating the detection outputs from said error detectingunit.
 2. A clock phase detecting circuit arranged in a receiving Areceiver circuit arranged in a receiving unit of multiplex radioequipment, comprising: an identifying circuit for identifying ademodulated signal at a predetermined identification level, saiddemodulated signal being obtained by demodulating a multilevelorthogonal modulated signal; a clock regenerating circuit forregenerating a signal identification clock for said identifying circuitto supply said signal identification clock to said identifying circuit;an equalizing circuit for subjecting said demodulated signal obtained bydemodulating the multilevel orthogonal modulated signal to an equalizingprocess; and a clock phase detecting unit for detecting a phasecomponent of said signal identification clock based on input and outputsignals of said equalizing circuit and then for supplying said phasecomponent to said clock regenerating circuit; wherein said clock phasedetecting unit comprising: an error detecting unit for detecting asignal error between said input and output signals of said equilizingequalizing circuit; a signal inclination detecting unit for detectingthe inclination of said demodulated signal; and a clock phasecalculating unit for operating the phase component of said signalidentification clock by calculating based on respective outputs fromsaid error detecting unit and said signal inclination detecting unit. 3.The clock phase detecting circuit arranged in the receiving A receivercircuit arranged in a receiving unit of multiplex radio equipment,according to claim 2, wherein said signal inclination detecting unitcomprising: a delaying unit for delaying the output from saididentifying circuit; and a comparing unit for comparing the output fromsaid identifying circuit with the output from said delaying unit todetect the inclination of said demodulated signal.
 4. The clock phasedetecting circuit arranged in the receiving A receiver circuit arrangedin a receiving unit of multiplex radio equipment, according to claim 2,wherein said identifying circuit is operated with high speed clocks; andwherein said signal inclination detecting unit comprising: a delayingunit for delaying the output from said identifying circuit, saiddelaying unit being operated with said high speed clocks; a latchingunit for holding the output from said identifying circuit and the outputfrom said delaying unit with clocks slower than said high speed clocks;and a comparing unit for comparing the output of said identifyingcircuit held in said latching unit with the output from said delayingunit to detect the inclination of said demodulated signal.
 5. The clockphase detecting circuit arranged in the receiving A receiver circuitarranged in a receiving unit of multiplex radio equipment, according toclaim 2, wherein said identifying circuit comprises plural identifyingunits corresponding to the number of plural demodulated signals obtainedby demodulating said multilevel orthogonal modulated signal; and whereinsaid signal inclination detecting unit includes a comparing unit thatcompares outputs of said plural identifying units with each other todetect the inclination of the demodulated signal when clocks withdifferent predetermined phase shift between said plural identifyingunits are supplied to said plural identifying units.
 6. The clock phasedetecting circuit arranged in the receiving A receiver circuit arrangedin a receiving unit of multiplex radio equipment, according to claim 2,wherein said clock phase calculating unit is formed as a multiplyingunit that subjects the output of said error detecting unit and theoutput of said signal inclination detecting unit to a multiplyingcalculating process.
 7. The clock phase detecting circuit arranged inthe receiving A receiver circuit arranged in a receiving unit ofmultiplex radio equipment, according to claim 2, wherein said clockphase calculating unit is formed as an exclusive OR calculating unitthat subjects the output of said error detecting unit and the output ofsaid signal inclination detecting unit to an exclusive OR calculationprocess.
 8. A clock phase detecting circuit arranged in a receiving Areceiver circuit arranged in a receiving unit of multiplex radioequipment, comprising: an identifying circuit for identifying ademodulated signal at a predetermined identification level, saiddemodulated signal being obtained by demodulating a multilevelorthogonal modulated signal; a clock regenerating circuit forregenerating a signal identification clock for said identifying circuitto supply said signal identification clock to said identifying circuit;an equalizing circuit for subjecting said demodulated signal obtained bydemodulating the multilevel orthogonal modulated signal to an equalizingprocess; and a clock phase detecting unit for detecting a phasecomponent of said signal identification clock based on input and outputsignals of said equalizing circuit and then for supplying said phasecomponent to said clock regenerating circuit; wherein said clock phasedetecting unit comprises: an error detecting unit for detecting an theinput signal to output signal error and output signals of saidequilizing equalizing circuit; a signal inclination detecting unit fordetecting the inclination of said demodulated signal; a clock phasecalculating unit for detecting the phase component of said signalidentification clock by calculating based on the respective outputs fromsaid error detecting unit and said signal inclination detecting unit; aspecific signal judging unit for judging whether a specific signalexists; and a gating unit for producting producing the phase componentof said signal identification clock obtained by said clock phasecalculating unit when said specific signal judging unit judges that saidspecific signal exists.
 9. The clock phase detecting circuit arranged inthe receiving A receiver circuit arranged in a receiving unit ofmultiplex radio equipment, according to claim 8, wherein said signalinclination detecting unit comprising: a delaying unit for delaying theoutput from said identifying circuit; and a comparing unit for comparingthe output from said identifying circuit with the output from saiddelaying unit to detect the inclination of said demodulated signal. 10.The clock phase detecting circuit arranged in the receiving A receivercircuit arranged in a receiving unit of multiplex radio equipment,according to claim 8, wherein said identifying circuit is operated withhigh speed clocks; and wherein said signal inclination detecting unitcomprising: a delaying unit for delaying the output from saididentifying circuit, said delaying unit being operated with said highspeed clocks; a latching unit for holding the output from saididentifying circuit and the output from said delaying unit with clocksslower than said high speed clocks; and a comparing unit for comparingthe output of said identifying circuit held in said latching unit withthe output from said delaying unit to detect the inclination of saiddemodulated signal.
 11. The clock phase detecting circuit arranged inthe receiving A receiver circuit arranged in a receiving unit ofmultiplex radio equipment, according to claim 8, wherein saididentifying circuit comprises plural identifying units corresponding tothe number of plural demodulated signals obtained by demodulating saidmultilevel orthogonal modulation signal; and wherein said signalinclination detecting unit includes a comparing unit that comparesoutputs of said plural identifying units with each other to detect theinclination of the demodulated signal when clocks with differentpredetermined phase amount between said plural identifying units aresupplied to said plural identifying units.
 12. The clock phase detectingcircuit arranged in the receiving A receiver circuit arranged in areceiving unit of multiplex radio equipment, according to claim 8,wherein said clock phase calculating unit is formed as a multiplyingunit that subjects the output of said error detecting unit and theoutput of said signal inclination detecting unit to a multiplyingcalculating process.
 13. The clock phase detecting circuit arranged inthe receiving A receiver circuit arranged in a receiving unit ofmultiplex radio equipment, according to claim 8, wherein said clockphase calculating unit is formed as an exclusive OR calculating unitthat subjects the output of said error detecting unit and the output ofsaid signal inclination detecting unit to an exclusive OR calculationprocess.
 14. The clock phase detecting circuit arranged in the receivingA receiver circuit arranged in a receiving unit of multiplex radioequipment, according to claim 8, wherein said specific signal judgingunit includes plural signal judging units that judge plural kinds ofspecific signals, and further comprising a selecting unit arrangedbetween said specific signal judging unit plural signal judging unitsand said gate gating unit, for selecting decision results from saidplural signal judging units.